I recall a Sophie Wilson talk about how things will never get faster, past 29nm.
For Server is it also about core count. For the same TDP AMD offer 64 Core option. On a Dual Socket System that is 128 Core. Zen 3 Milan is also socket compatible with Zen 2 Rome.
Basically for Server Intel has been stuck on 14nm for far too long. The first 14nm Broadwell Xeon was released in 2015, and as of mid 2021 Intel barely started rolling out 10nm Xeon Part based on IceLake.
That is half a decade of stagnation. But we are now finally getting 7nm server part, 5nm with Zen 4 and and SRAM Die Stacking. I am only hoping EUV + DDR5 will bring Server ECC DRAM price down as well. In a few years time we will have affordable ( relatively speaking ) Dual Socket 256 Core Server with Terabyte of RAM. Get a few of those and be done with scaling for 90% of us. ( I mean the whole StackOverflow is Served with 9 Web Server [1] on some not very powerful hardware [2] )
[1] https://stackexchange.com/performance
[2] https://nickcraver.com/blog/2016/03/29/stack-overflow-the-ha...
overall speed increases are still nothing like the old days and spectre style mitigations have been eating away at the improvements
I remember many, many years ago my PC couldn't run the latest adobe software as I was missing SSE2 instructions on my then current CPU. I believe there was some hidden compatability mode, but the software ran extremely poorly vs. the version of software that was out before that didn't require SSE2.
The microarchitectures have improved significantly though, which does matter. For instance, Haswell-era AVX2 implementations were significantly poorer than the modern ones in, say, Tiger Lake or Zen 3. The newer ones have completely different power usage and per-core performance characteristics for AVX code; even if you could run AVX2 on older processors, it might not have actually been a good idea if the cumulative slowdowns they cause impacts the whole system (because the chips had to downclock the whole system so they wouldn't brownout). So it's not just a matter of instruction sets, but their individual performance characteristics.
And also, it is not just CPUs that have improved. If anything, the biggest improvements have been in storage devices across the stack, which now have significantly better performance and parallelism, and the bandwidth has improved too (many more PCIe lanes). I can read gigabytes a second from a single NVMe drive; millions of IOPS a second, which is vastly better than you could 7 years ago on a consumer-level budget. Modern machines do not just crunch scalar code in isolation, and neither did older ones; we could just arbitrage CPU cycles more often than we can now in an era where a lot of the performance "cliffs" have been dealt with. Isolating things to just look at how fast the CPU can retire instructions is a good metric for CPU designers, but it's a very incomplete view when viewing the system as a whole as an application developer.
There always was an "Intel advantage" to compilers for decades (admittedly Intel invested in compilers more than AMD, but they also were sneaky about trying to nerf AMD in compilers), but with AMD being such a clear leader for so many years, I would hope at least GCC has started supporting AMD flavors of compilation better.
Anyone know if this has happened with GCC and AMD silicon? Or at least is there a better body of knowledge of what GCC flags help AMD more?
But in general I think it's a bit of a red herring for the thrust of my original post; first off you always have to target the benchmark to test a hypothesis, you don't run them in isolation for zero reason. My hypothesis when I ran my own for instance was "General execution of bog standard scalar code is only up by about 50-60%" and using the exact same binary instructions was the baseline criteria for that; it was not "Does targeting a specific microarchitecture scheduling model yield specific gains." If you want to test the second one, you need to run another benchmark.
There are too many factors for any particular machine for any such post to be comprehensive, as I'm sure you're aware. I'm just speaking in loose generalities.
Note that -march will use instructions that might be unavailable on other CPUs of the target. -mtune (which is implied by -march) is the flag that sets the cost tables used by instruction selection, cache line sizes, etc.
My test was a single threaded software rasterizer with real-time vertex lighting. That I compiled in vs c++ 2008 around 2010.
But the scalar speed isn't everything, because you're often not bounded solely by retirement in isolation (the system, in aggregate, is an open one not a closed one.) Fatter caches and extraordinarily improved storage devices with lots of parallelism (even on a single core you can fire off a ton of asynchronous I/O at the device) make a huge difference here even for single-core workloads, because you can actually keep the core fed well enough to do work. So the cumulative improvement is even better in practice.
And also that is the reason why I use such processor on my own computer, it was already "outdated" when I bought it, but since one of the things I like to do is play some simulation style games that rely heavily on single-core performance, I choose the fastest single-core CPU I could find without bankrupting myself. (the i5 4690k that with some squeezing can even be pushed past 4ghz, it is a beastly CPU this one)
We're near the end of IPC scaling per core. And it was never that good in the first place. Pentium 3 IPC is only 3-4x worse than the fastest Ryzen. Most of our speed increases came from frequency.
IMO we need to get off silicon substrate so we can frequency scale again.
I wonder if the end of scaling will push everyone into faster languages like Rust. You can't sit around 2 years for your code performance to double anymore. Will this eventually kill slow languages? I think so.
The arguable shift that is more significant is not about hardware its hopefully about newer languages like Rust making this performance cost less in terms of safety and development time which is a more recent development.
It's clear that's no longer true, which gives less excuses for using say Ruby over Java.
Think about it like the tempo of a song. The entire orchestra needs to play in sync with the tempo, but how many notes you play relative to the tempo is still up to each player. You can play multiple notes per "tempo tick".
We haven't had a strict clock speed = performance ratio for over a decade, it's just one component of it now.
https://en.wikipedia.org/wiki/Cycles_per_instruction
https://en.wikipedia.org/wiki/Instructions_per_second
Rather than just bumping clock speed, they've made improvements on what can be done within the clock cycle.
I recently did a desktop rebuild.
Went from a Ryzen 7 2700X to a Ryzen 5 5600X.
On paper, this looks like a downgrade. After all, the 7 is higher than a 5, right? I have two more cores with a 2700X...
However, the 5600x has about a 28% IPC gain over the 2700x in single core performance despite running at the same base clock speed. Literally 20%+ faster in the same tasks even when taking the turbo boost out of the equation.
The 2700x was at 12/14nm process while the 5600x is at 7nm which also helps with the power consumption as the 5600x has a 40 watt lower TDP.
Since what I need is better single core performance over more cores, the 5600X is quite an upgrade despite only being two years newer. (A LOT has happened in 2 years with AMD) With two less cores but significantly higher single core performance, the 5600X outperforms the 2700X on both single core and multicore performance.
Unfortunately for Intel, they did a lot of little tweaks and cheats to gain performance at the expense of security and now the mitigation patches pulls their chips back to the Bulldozer era in terms of current performance. They were also stuck at the same node for almost a decade now (Broadwell, 2014), so they had no gains from a shrink (speed of light propagation gain from a shrink, less heat and higher clocks also).
My i7-4790k is full of jank and microstuttering now, it has become unusable. Imagine how the servers might be doing if (and they should be) they are being kept up to date on security and microcode patches.
Then there also comes with spec upgrades within the processor generations. Ryzen 2700X to 5600X also means PCI Express went from 3.0 to 4.0... Not hugely significant among desktop users, but substantial for servers that need that amount of link bandwidth for compute cards and storage.
TLDR: Magic.
There are of course architectural improvements that improve performance with space to add gates etc, but when you have 1000s of chips cost of energy is the big thing.
I was blown away by how snappy and responsive the whole experience was compared to the then-not-bad Core2 Duo Grandpa had in his machine, running Windows 7 and Office 2010.
- You can mix chinese and russian characters in a document [pervasive use and support for unicode]
- Your computer won't get zombified minutes after you connect it to the internet [lots of security improvements]
- You can connect a random usb thingy with a much much lower probability of your computer getting instantly owned [driver isolation]
- You can use wifi with some reliability [more complex, stable and faster communication protocols]
- You can have a trackpad that doesn't suck [commodization of non-trivial algorithms/techniques that did not exist back then]
- Files won't get corrupted time and again at every power failure [lots of stability improvements]
Whether all of the above could be achieved with the _very performance oriented_ techniques and approaches that used to be common in older software is debatable at least. In any case, a lot of the slowness we pay for toady is in exchange of actually being able to deal with the complexities necessary to achieve those things in reasonable time/cost.
- Unicode text: All text consumes more memory (because the character space is much larger). Basic text processing ("wrap this paragraph at 80 characters") becomes much harder, not just because bytes != glyphs, but also because glyphs can combine.
- Security improvements: we now have various sandboxing, isolation, execution-protection, etc.. features in OSes. The performance impact of some of those is negligible thanks to new hardware features to help with them, but others still have a significant cost. Furthermore, some performance tricks used in old systems would simply violate the current security models and are hence impossible to do anymore.
- Driver isolation: this is similar to the above. The OS is now doing more work to ensure drivers behave, the isolation forbids some more performant pathways, etc.
- Wifi with some reliability: this was an example of progress being achieved. Wifi protocols are a nightmare, and I'm still amazed that they work at all.
- Better trackpads: another progress example. The big issue here has been the development of smarter algorithms (and the hardware refinement to back them up). This is something that seems simple, but it took a very long time to get this anywhere acceptable (even after Apple showed the world it was possible). I can only assume that it is actually a pretty hard problem underneath.
- Files that don't get corrupted: we have needed years and years of iterative improvements to finally get here, both at the FS level and on the programs above (think DBs). We are now going through journal logs, memory barries, checksumming and verifying data, using copy-on-write for FSs, etc.. All these things have non-negligible runtime and camplexity costs.
In general, we have been prioritizing to make more stuff and/or making the stuff more correct, disregarding the performance aspect so long as it remains good enough (from the POV of the developers).
Everyone agrees that M1 is a very fast chip, much faster than the current Intel chips shipping with Macbooks.
And yet: when I trigger the native "Open File" dialog from IDEA, it still takes MacOS up to a second to verify permissions on a list of directories and mark them as available.
So, given that:
- M1 is blazingly fast
- modern SSDs pump GBs of data per second
- RAM on M1 is almost literally a part of the CPU, and the bandwidth of modern RAM is also GBs per second
why does it take up to a second to verify permissions on a list of five directories?
> Unicode ... Wifi ... Trackpads ...
None of these require GBs of RAM and 16-core processors to barely run.
Go on...
This is also debatable at least.
Just a few weeks ago it turned out that the new Windows Terminal can only do color output at 2fps [1].
The very infuriating discussion in the GitHub tracker ended up with a Microsoft tea member saying that you need a " an entire doctoral research project in performant terminal emulation" to do colored output. I kid you not. [2]
Of course, the entire "doctoral research" is 82 lines of code [3]. There will be a continuation of the saga [4]
And that is just a very small, but a very representative example. But do watch Casey's rant about MS Visual Studio [5]
You can see this everywhere. My personal anecdote is this: With the introduction of new M1 macs Apple put it front and center that now Macs wake up instantly. For reference: in 2008 I had the exactly same behaviour on a 2007 Macbook Pro. In the thirteen years since the software has become so bad, that you need a processor that's anywhere from 3 to 15 times more powerful to barely, just barely, do the same thing [6].
The upcoming Windows 11 will require 4GB of RAM and 64GB of storage space just for the empty, barebones operating system alone [7]. Why? No "wifi works reliably" or "trackpad doesn't suck" can justify any of this.
[1] https://twitter.com/cmuratori/status/1401761848022560771
[2] https://github.com/microsoft/terminal/issues/10362#issuecomm...
[3] https://twitter.com/cmuratori/status/1405356794495442945
[4] https://twitter.com/cmuratori/status/1406755159347130371
[5] https://www.youtube.com/watch?v=GC-0tCy4P1U
[6] https://gadgetversus.com/processor/apple-m1-vs-intel-core-2-...
[7] https://www.microsoft.com/en-us/windows/windows-11-specifica...
This uses all the constraints that the Windows terminal team cited as excuses: it uses Windows subsystems etc. One person, 3k lines of code, it runs 100x the speed of Windows terminal.
See the epic demo (and stay till the end for color output): https://www.youtube.com/watch?v=hxM8QmyZXtg
- Yeah, some lower-level stuff seems to be broken (the windows console I/O stuff).
- Microsoft's devs linked to a very nice website that quickly and nicely explains some of the quirks of modern text rendering [1].
- Casey proceeds to demonstrate a (very fast!) approach that completely ignores some of the problems laid out in that site. Namely, his entire approach is based on caching rendered glyphs, which the document explicitly states is something you can't do naively and expect correct results (section 5).
- In his very demo some of these issues pop up (terrible-looking emojis, misaligned ascii art) and he shrugs those off as if they were easy jobs.
- Other issues are never tested in his demo. Examples include: (i) dealing with text selection, which is hard according to the linked site; (ii) how is he "chunking" non-asscii character runs (also hard to do correctly); (iii) handling ligatures (terminal programs oftentimes use ligatures between basic ascii character combinations such as => to make some source code more readable)
In other words: I see an incomplete solution that addresses only the easy parts of the problems (in a very performant way!) that fundamentally cannot be extended to a correct solution for the actual/full problem. And a lot of arrogance while presenting it.
In no way does this mean that a much more performant solution doesn't exist. But Casey's cute demo is not a proof that it does because it does not solve the actual/full problem.
PS: I don't work for MS, I don't know Casey nor any of MS's devs, and I don't even use windows. I do hold a PhD though, and I know plenty of PhD's dedicated to exploring the nitty-gritty details that some people with only cursory knowledge about the problem would dismiss as "this must be a quick job".
But very slightly less naively you can get correct results. One trick is to realise that ClearType only increases the effective horizontal resolution. Also, despite appearing to have three times the horizontal texels available to it, the final post-processing to reduce the colour artefacts means that the effective resolution increase is only about double the pixel count. So you can get very good results by horizontally stretching your glyph cache buffer by a small factor, typically three. This is not a huge increase in memory usage, and provides more than sufficient subpixel positioning quality. Where this breaks down is if your pipeline has very complex text special effect support, such as arbitrary transforms.
But a terminal emulator needs very few special effects. It doesn't need to be rotated smoothly through arbitrary angles, which DirectText supports. It doesn't need perspective transforms, or transparent text, or a whole range of such exotic features.
In fact, 99.99% of the characters drawn by a terminal emulator will be plain ASCII aligned to a simple grid. This is a trivial problem to solve, as demonstrated in this thread. It's not PHD work, it's homework.
Remember: this is a demo written by one person over a few days, and not, you know, a full team of people at a multi-billion-dollar corporation.
> Microsoft's devs linked to a very nice website
> some of these ... hard according to the linked site ...
1. It's more excuses, and 2. we are not talking about "everything on the website".
He took all the constraints that the Windows terminal team imposed (you have to use DirectDraw, you have to go through conio, you have to use the unicode subsystem in Windows), and:
- even using those constraints he sped up the terminal 10x
- he already does things than windows terminal doesn't, for example: correct Arabic with correct ligatures despite "omg this website shows why it is so hard". So yes, he caches glyphs, and still displays proper Arabic text (something Windows terminal doesn't do) with varying widths etc.
And that 10x speedup? Instantly available to Windows terminal if only they use a cache of glyphs instead calling DirectDraw on every character. This is not rocket science. This is not "phd level research thesis". This is just junior-student-level work.
As to the issues:
- he was the very first one to point them out because he a) knows about them and b) knows how to solve them
- yes, the solutions he proposes are easy: the main "issue" is DirectDraw improperly handling font substitution, and his proposed solutions (resample glyphs after draw or skip DirectDraw and write your own glyph renderer) are easy. He literally does that for a living.
- omg text selection. Yes, text selection is a hard problem. But it's not an impossible problem, and nothing about text selection should bring the renderer from 5k fps to 2fps
> some people with only cursory knowledge about the problem would dismiss as "this must be a quick job"
These are not "nitty-gritty" details. And they are definitely not from a "person with cursory knowledge". There's nothing new in terminal rendering.
"As an online discussion about software bloat grows longer, the probability of a Casey Muratori rant being posted approaches one."
That is not "the software" unless you count EFI, the sleep process is mostly a hardware thing and controlled by Intel.
Core 2 Duo was introduced 15 years ago (2006). Almost a decade before Windows 10 was released.
Windows 10, and all modern operating systems, are designed around the availability of modern GPUs. If you try running it on an ancient machine without modern graphics acceleration and without enough CPU power to handle it in software, it's going to feel sluggish.
Windows 10 is perfectly fine and snappy on every machine I've used it on in recent history.
And then you can also think about the security improvements.
I also don't see why the security improvements lead to such a massive decrease in performance.
What's still increasing is transistor density, but "Dennard's Scaling" is dead. we stopped decreasing voltages some time ago.
We have more transistors, so we can make smarter chips. but we can't turn them on at the same time ("dark silicon"), we don't want to melt the chips.
Short of using other materials such as GaN, frequency won't really go above 5 GHz.
There remain plenty of ways to improve performance though: improvements to system architecture (distributed, non von neumann, changing the ISA), compilers, etc. Adiabatic computing, 3D integration, carbon nanotubes, tri-gate transistors, logic in memory, "blood" (cooling + power) and other microfluiduc advances, modularization with chiplets.
The "simple" Dennard's scaling is over though, and we need to move beyond CMOS and Von Neumann to really leverage increasing density without melting away.
A quick perusal of WikiChip seems to suggest that this isnt true. Pretty much everything is getting smaller, including Fin pitch which should directly affect transistor size (not an EE, certainly could be wrong there). You're absolutely right that terms like "7nm" have become decoupled from a specific measurement and are largely marketing terms, though.
Everybody says this, if I've read it once on HN, I've read it a million times.
But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.
Well, I looked up and calculated this for several chips/processes, and I found that the number was consistently around 10 times the published figure, in nm.
The further interesting thing I discovered is that this seemed to go way back with no particular change in the ratio.
So it appears to me that the "decoupling" of the number from reality is a myth; it's not "real" but it's the same ratio it's always been.
But then, there's no obvious (to me) reason why a realistic number is out of the question, either.
Exactly, as that's more or less what "process node" refers to today. I guess they don't want to change the metric as some could be confused by it.
> But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.
There are plenty of other metrics. As usual, measuring only one number hides half the story. A process node is characterized by gate leakage and capacitance among others, for the electrical characteristics. Then, more meaningful surface area metrics are the size of an actual logic cell, like SRAM or a flipflop. Some processes lend themselves to optimizations that wouldn't be visible if just placing transistors side by side.
Transistor size (occupied area) decreases, but that's mainly because FinFET uses vertical gates, not planar technology, so you can stack them closer (well, it also has other advantages).
Thanks for the links, that's an interesting website. If you look at the 10nm one, they explicitly call out what I said, and write 20nm for gate length (tunneling losses start increasing a lot if you reduce that, so I'm not sure how to read the 7nm page, maybe they got it wrong?)
In any case, process node once reffered to gate length; it doesn't anymore: https://en.wikichip.org/wiki/technology_node
We're not getting smaller, not that we couldn't (e-beam and ALD give us atomic resolution), but because it's useless (at that point, gate leakage and doping issues become hard to overcome). Instead we're improving precision, and our control along the 3rd dimension. Integration technologies are also progressing: flip-chip, TSVs. That will allow features like integrated HBM, on-chip lasers and photonics circuits, etc.
In case anyone missed it, AMD announced a basic "3D" design last month
https://www.hpcwire.com/2021/06/02/amd-introduces-3d-chiplet...
Essentially AMD "stacked a 64MB 7nm SRAM directly on top of each core complex, tripling the L3 cache available to the Zen 3 cores."
I am excited to see what comes next!
Process engineers&material scientists seem more cautious. I'm sure shrinking goes but gains are smaller from each generation.
TSMC 3nm Process is something like 250 MTr/mm² and single digit performance increase and 15-30% power efficiency increase compared to older prosess.
Performance increases from generation to generation used to be much faster. TSMC's N16 to N7 was still doubling or almost doubling performance and price/performance over the long term. N5 to N3 is just barely single digits.
Every fab generation is more expensive than in the past. Soon every GIGAFAB costs $30 billion while technology risk increaseses.
Not sure that is really true based on the data. Remember, Moore's law says the number of transistors in an IC doubles every two years, which doesnt necessarily mean a doubling of performance. For a while in the 90's, performance was also doubling every two years, but that was largely due to frequency scaling.
https://upload.wikimedia.org/wikipedia/commons/0/00/Moore%27...
A lot of the new processes have not had the same cost reductions. Also, some increase in transistor count is due to physically larger chips. Also, you have “Epyc Rome” on that graph, which actually isn’t a single chip but uses chiplets.
The first one built will get cheaper to run every year - it will pay for itself by the time a second company even tries to compete. The first person to the "final" node will have a natural, insurmountable monopoly.
You could extract rent basically forever after that point.
Consider other mature technology, like the internal combustion engine. ICEs have been improved continuously, though the changes have become marginal as the technology matured. However, if research and improvements on ICEs ends entirely it's not because the technology has been fully explored but because they're obsoleted by electric cars.
https://www.youtube.com/watch?v=naed4C4hfAg
At 1:20:00
David Patterson is saying he considers Moore's Law is dead because the current state of say, "transistor count doubling every three years" doesn't match the Moore's Law exact statement.
In other words, he is simply being very pedantic about his definition. I can see where he's coming from with that argument.
The rough organizational structure of a VLSI team that makes CPUs is the following pipeline:
architecture team -> team that designs the circuits which implement the architecture -> team that manufactures the circuits
The law was a message to the architecture team that by the time your architecture gets to manufacture you should expect there to be ~2x the number of transistor you have today available, and that should influence your decisions when making trade-offs.
And that held for a long time. But, if you're in a CPU architecture team today, and you operate that way, you will likely be disappointed when it comes to manufacture. Therefore one should consider Moore's law dead when architecting CPUs.
The good times might be back for now - and don't get me wrong, I'm having a blast - but don't expect them to last for long. I think this is probably the last sputter of gas in the tank, not a return to the good times.
Computers are the most complex objects man has created, there is no way it is going to be finished.
actually if companies and software were designed differently (with teaching too, basically an ideal context) you could improve a lot of things with 10x factors just from the lack of resistance and pain at the operator level
A simple example for me is how the ATM replaced the bank teller, but the ATM has been replaced with cards with chips in them. It’s a subtle, but huge change when magnified across society.
having worked in various administrations, the time / energy / resources wasted due to old paper based workflow is flabbergasting
you'd think after 50 years of mainstream computing they'd have some kind of adequate infrastructure but it's really really sad (they still have paper inbox for internal mail routing errors)
I could definitely see standard classical computer hardware becoming a commodity though.
There will also be room for horizontal expansion for a LONG time. If costs drop through the floor then we could see desktops and servers with hundreds or thousands of 1nm cores.
We probably have a way to go yet but the CMOS process shrink curve was a pretty magical technology advancement that we may not see again soon.
Java is only just now getting value types, even though flattened value types are fundamental to getting good performance on modern CPUs. Much software is HTML and JavaScript which is so far from having value types it's not even worth thinking about. Simply recoding UIs from JS -> Java/Kotlin+value types would result in a big win without much productivity loss.
Away from the IC level itself we're only just starting to scratch the surface of optimisation algorithms for many NP-hard problems that occur in IC design, like floor plan arrangement.
Include longevity as one of the points of comparison and a lot of progresses looks like a step back. Cheaper and doesn’t last as long has been a tradeoff people have been willing to make for thousands of years.
Babies have "colics", which are probably some kind of pain that we haven't identified yet, but because they go away on their own and parents are taught that they just have to deal with them, we still apply a medieval solution to the problem ("tough it out").
Rings seem to be the kind of problem where our current solution is good enough.
I don't foresee computing power to be the same. We'll want more and more of it.
So stagnation will be due to gaps in basic research, not due lack of interest.
I do believe there will be stagnation unless a different way is found. In the same way Henry Ford said people wanted a faster horse not a car.
And regarding travel, I would like to have faster, much faster transportation. However it hasn't come, yet. There seems to be a local optimum between costs and practicality.
What about advancements metallurgy? And to use an adjacent example, cold-pressed steel techniques increase the number of places steel can be used. (See here https://en.wikipedia.org/wiki/Cold-formed_steel#Hot-rolled_v...).
More often that not, technology enables trade-offs to be made that couldn't be before. Making something cheaper and more fragile does lose something, service life, and so on. In exchange the cheaper thing is now used more widely. Perhaps this more widespread use unlocks something that only a few expensive yet high-quality units could not. Think of smartphones and the resulting network effects.
Remember those days? When every server upgrade magically sped up everything by a factor of two or three? The stop button was pressed on that wonderful time for about a decade, but what seemed like an end of an era wasn't. It was just a pause, and now we're playing with ever faster tin once again.
It feels almost strange for that era of ever increasing hardware speed to make such a forceful comeback after having been stuck at Intel 14nm in the server space for years. The upgrades to 7nm AMD are already pretty impressive. I hear good things about Apple's 5nm laptop chips. Server chips on 3nm should blow everyone's frigging minds.
Exciting times!