Nokinside

They don't attempt to jam, the frequency is just little bit off to minimize damage and it's very short time. They just test the system to verify that it works.

What this reveals: Russian early warning satellite constellation has also GNSS jammers they test periodically. They can jam whole continent from single satellite. They have six satellites in Molniya orbits.

Sounds familiar. If one of the authors Lemire? Of course.

SIMD-accelerated integer-to-string conversion https://lemire.me/blog/2026/05/18/simd-accelerated-integer-t...

Other speedy things:

On-Demand JSON: A Better Way to Parse Documents? https://lemire.me/en/publication/arxiv231217149/

Parsing Millions of URLs per Second https://lemire.me/en/publication/arxiv231110533/

Transcoding Unicode Characters with AVX-512 Instructions https://lemire.me/en/publication/arxiv221205098/

Because we want to write correct code. We want to verify the absence of many types of errors where amateurish language war stuff like Rust vs C does not even scratch the surface.

I would propose that we change your original statement "Ideally neither C nor C++ should be used when security matters." into:

"Ideally people who don't care about secrurity should not write code when security matters."

Can we agree that this is better than talking about programming languages?

Explain to someone like me who uses C in safety-critical software in aerospace and defense why not?

For me, choosing the language is not enough. It's the tooling that goes far beyond the language that is important for safety and quality of compiler and runtime. C has very mature tooling options. So does ADA.

https://www.absint.com/astree/index.htm

Abstract Interpretation in a Nutshell https://www.di.ens.fr/~cousot/AI/IntroAbsInt.html

It's remaining and rearrangement of the same stuff. Not a new feature.

The first SoC including Neural Engine was the A11 Bionic, used in iPhone 8, 8 Plus and iPhone X, introduced in 2017. Since then, every Apple A-series SoC has included a Neural Engine.

The first SoC including Neural Engine was the A11 Bionic, used in iPhone 8, 8 Plus and iPhone X, introduced in 2017. Since then, every Apple A-series SoC has included a Neural Engine.

That's just start.

The bleeding edge uses abstract interpretation to verify code.

Free from NASA: IKOS (Inference Kernel for Open Static Analyzers) is a static analyzer for C/C++ based on the theory of Abstract Interpretation. https://github.com/NASA-SW-VnV/ikos

Commercial: Astrée is a static analyzer for safety-critical software written or gen­er­ated in C or C++. https://www.absint.com/astree/index.htm https://www.absint.com/astree/index.htm

abstract interpretation for static analysis and verification:

Good intro Mechanized semantics, fifth lecture Abstract art: static analysis by abstract interpretation https://xavierleroy.org/CdF/2019-2020/5.pdf

Static Analysis and Verification of Aerospace Software by Abstract Interpretation https://mine.perso.lip6.fr/publi/article-bertrane-al-fntpl15...

It'll be the same for Intel with their new process node.

Everyone working with the latest process node is tightly coupled with the manufacturer: Nvidia, Apple, AMD, and Qualcomm. Microarchitecture design and optimization for a new process is super expensive and hard.

Legacy processes have settled, have standardized design software and tooling, so everything costs less.

ps. Nvidia and Qualcomm are considering Samsungs 2mm because TSMC's 2-nanometer chip production capacity is extremely limited.

Software verification tools based on abstract Interpretation are really good today.

If you want free software I recommend IKOS - a is a sound static analyzer for C/C++ developed at NASA. Checks: https://github.com/NASA-SW-VnV/ikos/blob/master/analyzer/REA... Numerical abstract domains: https://github.com/NASA-SW-VnV/ikos/blob/master/analyzer/REA...

Commercial tool like Astree https://www.absint.com/astree/index.htm if you have money.

Few years back suspected Israeli IMSI-catcher was fond in DC https://www.politico.com/story/2019/09/12/israel-white-house...

APNewsBreak: US suspects cellphone spying devices in DC https://apnews.com/general-news-d716aac4ad744b4cae3c6b13dce1...

It's common to discover IMSI-catchers in national capitals around the world. There are many interesting targets.

Washington, D.C. mobile traffic is probably the most spied in the world. Especially now when it's run by technological cavemen and overly confident techbros. Israeli, Russians, Chinese, French and everyone.

> least some part of the populace is well armed enough to overthrow t

What a naive fantasy.

Organization of people is much more important than guns. You don't even need guns when you organize. You can stop the state just by collective action. See color revolutions.

When it is guns, you need RGP's, detonators and TNT (and drones), a good underground insurgent logistic chains. You also need commit to life in poverty and eventual death.

United States, Hungary, Turkey, Russia, Serbia have plenty of independent weapons, yet there is no fear of effective armed resistance. Everybody is a rebel in the Internet. When things go tough it's "I have to go to work and eat. My family needs me."

It was just a question of time.

Even without spoke-and-hub model, hubs grow and there are more hubs. Airports are the bottleneck. 500 passengers per landing adds capacity.

I belong to the same X-gen group as Marc Andreessen, Curtis Yarvin, Elon Musk,Peter Thiel, and others. I have a background in computers and am financially independent.

While I strongly disagree with them, I feel an affinity and familiarity with their thinking. I have read the same books, seen the same news, and lived in the same era. I understand how they arrived where they are now.

The Neo-reactionary movement seems exactly like what my generation comes up from the right. Dark Psychology of Dark Enlightenment is a cyberpunk sci-fi world as a fantasy. To live with societal collapse, dystopia and decay with low-life and high-tech. Always framing oneself as an independent outsider and a rebel. Sarcasm as a reflex. These guys see themself living in William Gibson's Neuromancer world.

They use the whole wafer for a chip (wafer scale). The WSE-3 chip is optimized for sparse linear algebra ops, used 5nm TSMC process.

Their idea is to have 44 GB SRAM per chip. SRAM is _very_expensive_ compared to DRAM (about two orders of magnitude).

It's easy to design larger chip. What determines the price/performance ratio are things like

- performance per chip area.

- yield per chip area.

I have been looking at their patents. Seems well defended and methodological. Someone like Intel, Nvidia or AMD might buy them soon.

Speedup is realistic. Multicore SMP or NUMA are not good for memory access patterns they optimize.

Their thick control flow model that should work for exclusive matrix-addition and log-prefix style memory access patterns. In comparison to the baseline the speedup is 150% in log-prefix algorithm, over 190% in fft-style butterfly algorithm, 50-100% in matrix addition and threshold filtering. silicon area and power consumption are estimated to be low.

Light reading material:

Optimizing Memory Access in TCF Processors with Compute-Update Operations Optimizing Memory Access in TCF Processors with Compute-Update Operations https://ieeexplore.ieee.org/document/9150423

The REPLICA on-chip network https://ieeexplore.ieee.org/document/7792877/

Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors https://ieeexplore.ieee.org/document/10305463/

Realizing multioperations and multiprefixes in Thick Control Flow processors https://linkinghub.elsevier.com/retrieve/pii/S01419331230005...

Biboys sold for near $50 million to ATI, then it was sold to Qualcomm.

This is how most semiconductor startups work. Do better and show innovation that is bought buy bigger players.

Pro tip: If you want to know who is the king of AI chips, compare FLOPS (or TOPS) per chip area, not FLOPS/chip.

As long as the bottleneck is the fab capacity as wafers per hous, the number of operations per second per chip area determines who will produce more compute with best price. It's a good measure even between different technology nodes and superchips.

Nvidia is leader for a reason.

If manufacturing capacity increases to match the demand in the future, FLOPS or TOPS per Watt may become relevant, but now it's fab capacity.

If I remember correctly Caltech is in the quality over quantity group as well. Something like 100 - 150 graduates per year.

Here is some data:

CHIPPING AWAY ASSESSING AND ADDRESSING THE LABOR MARKET GAP FACING THE U.S. SEMICONDUCTOR INDUSTRY https://www.semiconductors.org/wp-content/uploads/2023/07/SI...

>67,000, or 58%, of new jobs across manufacturing and design will risk going unfilled by 2030.

Another nugget from Fig 6: More than half of the MS graduates in semiconductor-related engineering fields are foreign and 80% of foreign Master’s leave the U.S.

People in the US keep asking "Should I go to college?" and "Who needs calculus?"

Maybe it's not just the wage cap.

There is plenty of semiconductor industry in the US but it's differently specialized and they compete for the same pool of engineers. Nvidia, AMD or Broadcom don't have fabs, but they hire engineers from the same pipeline as fab companies.

It's few years since I was hiring EE majors in the US, but it felt that skilled people with EE master's are harder and harder to find every year. I think USC and CMU are the only ones that produce quantity and quality. MIT, Stanford, and Berkley produce quality but not quantity.

>There is a huge AI chip shortage right now, so basically, every big AI player has some kind of chip program going.

Mostly bike-shedding. Designing new architectures for older generation technology nodes adds some capacity, but does not help with the bleeding edge.

The shortage is in fab level. There are multiple bottlenecks. ASML has $36 billion backlog. There is not enough advanced packaging available. Hybrid bonding machines are in short supply. This technology requires lithography-level clean rooms (ISO 1 or ISO 2),and surface smoothness. Die-to-wafer hybrid bonding for large logic is currently very expensive.

6nm and 7nm technology nodes and 100k WSPM capacity. Other investors are Sony, Toyota, and Denso, they will also be main customers.

Taiwan already has a fab in japan 40 nm, 28 nm, 22 nm, 16 nm, and 12 nm process technologies working with 55k WSPM capacity.

Similar specs and price as XR-4 from https://varjo.com Wipes the floor with Oculus and others, but IMHO 90Hz refresh rate not enough for truly immersive VR/AR experience.

Once the initial fascination wears out, you are not going to use it as replacement for the big screen. VR/AR needs improve technically and find killer apps and must-have games.

I would be interested to know about their executive function and self-regulation skills. The ability to plan, focus attention, remember instructions, working memory, mental flexibility.