As already mentioned, there's plenty of innovation happening still with packaging, plus even on the IC level there's all kinds of possibilities for advancement: new transistor designs (to reduce power consumption or to increase density by decreasing spacing), monolithic 3D ICs (the vast majority of current 3D approaches are manufacturing multiple wafers or dies then wiring them together; if you can do it on a single wafer you can do a lot more movement between layers). Plus there's always the potential to move away from silicon to make transistors even smaller.

Away from the IC level itself we're only just starting to scratch the surface of optimisation algorithms for many NP-hard problems that occur in IC design, like floor plan arrangement.