In fact, the node number has never referred to transistor dimension, but the length of the gate electrode. A transistor would typically be about 4 times larger than that.
The reason to refer to the length of the gate electrode is because that was always the smallest feature printed on the chip. And that is what defined the required resolution of the lithography process.
So, a lithography process with a resolution of 32nm would be able to print chips with 32nm gate lengths.
Much has changed, and now transistors are no longer planar, they are 3-dimensional fin structures (FinFETs). The gate length scaling has slowed down, and now is not the smallest feature on the chip anymore.
The smallest feature in a modern FinFET process is actually the with of those 'fi s' that form the transistor channels.
And as if by magic, they correspond pretty well to the node names, i.e. a 5nm process will have a fin width of about 5nm.
You will likely not find that mentioned anywhere, it's just a fun fact that I noticed as a VLSI technologist.
I also just checked a handful of processes I have access to, and at least in these cases, the fin width doesn't scale with the technology name (e.g. 5nm and 7nm has 8nm fin width drawn in layout, and model indicates 27nm "width" per fin). This isn't much of a surprise to me, because foundries are just decreasing the number with newer generations of the tech, even if the lithography (the method by which features are etched into the silicon) hasn't significantly changed. For example, 3 generations of a single process were called 7***, then 5***, then 4***.
That's your bias. To a process engineer the parameter that matters is what wavelength you are blasting the mask with and what size a feature it can create.
These processes are not exactly standardised either it would be a major undertaking to take an architecture from TSMC 7nm to 5nm let alone moving from TSMC to Samsung, Global Foundaries or if at all possible Intel.
Not unlike how there are pipeline phases that are just a little longer than they theoretically could be (because all of their neighbors have to line up with each other). If you can fix the bottleneck then everything else can shine, causing a magical, outsized improvement.
To make further progress designs had to be changed, and things have gotten fuzzier. Processes from different foundries have different densities. Intel's process for a given node is denser than that of the big foundries like TSMC.
See https://en.wikichip.org/wiki/technology_node for more on this.
Improved semiconductor device density directly translates into benefits for more advanced computing systems— the primary driver for progress in semiconductor technology. Thus, we propose the use of the following three-part number as a metric to gauge advancement of future semiconductor technologies: [DL, DM , DC ], where DL is the density of logic transistors (in #/mm2), DM is the bit density of main memory (currently the off-chip DRAM density, in #/mm2), and DC is the density of connections between the main memory and logic (in #/mm2). As an example, today’s leading edge technologies that are published in the literature [15]–[17] can be characterized by [38M, 383M, 12K]. As another example, 3-D stacking of multiple logic and memory dies can increase DL, DM, and DC .
Not as cool as megaFonzies.
(still bitter about the whole GB vs GiB think caused by marketing people)
Deciding that in your field you're going to redefine standard units and their abreviations is a bit lazy.
Perhaps it would be better to go with "6502s per square millimeter" or something like that that would probably be a closer approximation of real-world density, since it accounts for wire routing and so forth.
SRAM density is sometimes used I think.
(Apollo Guidance Computer)
edit: The product blurb says it’s an induction motor. The nameplate says 1000W. It would be fairly straightforward to estimate the efficiency by blending a known amount of water and measuring the temperature change over some period of time.
In fact, the draw varies enough during the cycle that it’s a well known method in industrial ecology to put a condenser on a 60Hz motors when the supply is 50Hz. So there must be a visible cycle.
Whether the measurement method is appropriate to your use of an amplifier is of course anybody's guess.
I agree the term "RMS" is kinda miss-appropriated, but it's short and tends to understood as something reasonably close to what it's actually about.
Accurate RMS can easily be calculated and advertised. Check out Steve Meade and his tools/videos if you're unaware.
Most prominent brands just choose to market absolute bullshit numbers - people who know what they're actually after know how to find the brands who publish real numbers.
For comparison, sheet goods aren't priced this way. A 3/4" sheet of plywood really is 3/4", because the plywood was manufactured that way and as a manufactured product there is no seasoning.
You're not being ripped off because a 2x4 is actually smaller. A sawmill had a tree, and they cut off a hunk of that tree, and they charge by how much wood they cut off. The dimensions of that piece of wood changed after they cut it (which in and of itself is a service they provide - it would be a hassle if you had to buy green lumber and dry it yourself).
It's interesting that lumber kind of looks like shrinkflation (what the comment I was originally responding to suggested), but it's more that technical improvements have allowed producing the same finished product with less input material. But we still label the stuff by the amount of input material it used to take for historical reasons, which at a glance looks like shrinkflation.
And what's is worse is how hard it is to know the true size of everything you find in stores in the USA. The same applies to pipes of all types. But even things like a drawer slide is often not the advertised length. Saw blades thinkness is converted from 2.5mm to whatever the closest inch the salesperson felt that day.
From having spent quite a lot of time in big box stores in France and the USA. I can tell you that in the USA 3/4" (19mm) can be anything from 16mm to 24mm.
In short almost everything is built in metric and the USA likes to pretend it's not and gets confused by rounding up randomly.
3/4 plywood will measure less than 3/4.
So, TSMC is not really that far ahead after all? 28 nm is like a decade old now?
This sounds like women’s vanity sizing. Size 6 is now Size 0.
Jesus, this is the height of arrogance...
Wendell Wilson isn't qualified to talk about this?
Linus Sebastian isn't qualified to talk about this?
Dr. Ian Cutress isn't qualified to talk about this?
I would listen to all three of those before I listen to anything you say.
1500W PSU!!! But you'll never know how we came up with that figure!
It's refreshing to see this mentioned. I'm no semiconductor expert, but it seems weird to me that although node size is measured in a physical unit, nanometers, it does not correspond to any real measurement that exists [1]. Each transistor in a 5nm chip is actually between 28 and 36 nanometers in width. It's called 5nm because of a theoretical calculation based on transistor density [2].
If Tesla advertised a new "200kWh" battery, I would be very disappointed if it turned out that the battery only held 95kWh, but the marketing department had decided that improvements in the charging network have made it "like 200kWh" compared to earlier models.
[1] https://en.wikipedia.org/wiki/5_nm_process
[2] https://en.wikichip.org/wiki/technology_node#Meaning_lost