So essentially the 'node' size is the lithography process, not the chips you design with that process. You can't make a feature smaller than the lithography process, nor x.5 times as big as the resolution of the lithography. There will then be a bunch of parts of the chip that are just a little bigger or a little farther apart than they need to be.

Not unlike how there are pipeline phases that are just a little longer than they theoretically could be (because all of their neighbors have to line up with each other). If you can fix the bottleneck then everything else can shine, causing a magical, outsized improvement.