The node size never referred to the actual size of the transistors. Back in the days when CMOS scaling was simple, it referred to the half-pitch, half of the center-to-center distance of the Metal 1 lines. The gate length was roughly the same, usually. But scaling had to be changed starting in roughly 2003 because atoms don't scale; the joke was that transistors were no longer switches, but just dimmers, because leakage was an increasing problem. Designs could no longer be simply scaled, producing a faster clock cycle for free; they had to be revised, and a FinFET looks very different from a traditional FET.

To make further progress designs had to be changed, and things have gotten fuzzier. Processes from different foundries have different densities. Intel's process for a given node is denser than that of the big foundries like TSMC.

See https://en.wikichip.org/wiki/technology_node for more on this.