>so a feature with 3nm width

Sigh, another post... another top comment not understanding that marketing name =/= any actual feature size anywhere on the chip.

I've been reading threads like this for 10+ years now, and somehow this knowledge has still not permeated the tech culture here and on reddit.

Once upon a time (the "Dennard Scaling Era") VLSI circuit design used the same relative geometry at different "feature sizes" - all dimensions of the design(wire width, wire spacing, gate length, gate pitch, ..., etc.) scaled by the same amount from generation to generation, so it was possible to completely specify the transistor layout with a single dimension (generally called 'L'), and derive all other measurements from that as a multiple of 'L'. Transistor density was proportional to 1/L^2.

The measurement that was used originally for 'L' was the gate length.

As designs shrunk below 40nm, it became impossible to shrink _every_ dimension proportionally. In particular, for planar silicon, gate length stops shrinking around ~30nm, but other things could still shrink. This meant that transistor density could still increase, but the relative geometry of wires/gates/spacing/etc. had to change, so it was no longer possible to specify the full geometry with a single number.

But people liked the single number as a handy way of comparing processes, so marketing kept using it as a way to compare processes. The way they decided to do that was mostly to try and keep the proportionality between the transistor density of a process and 1/L^2.

To the extent a "feature size" number of a process means anything, it means "the relative transistor density of this process is equivalent to what you would get if you had used the old (>40nm) geometry, and shrunk 'L' to the specified feature size". Even that relationship has degraded in recent years - now it's more like "we calculate the new feature size as the size of the previous process divided by sqrt(2)".

Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number.

There's lots of resources online that describe this, but for an overview, you could start here (describes pre- and post-Dennard scaling): http://www.eng.biu.ac.il/temanad/files/2017/02/Lecture-4-Sca...

Nice explanation. One can see an example of the scalable CMOS design rules on slides 10 and 11 of this deck.

https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pd...

(To the casual reader: Note how the dimensions all have no unit. There are measured in L as indicated by the parent.)

Thanks for that explanation.

What would be even more useful is an actual answer to the underlying question the OP seems to be making: how much further until one of the many dimensions you are talking about simply runs out of Si atoms?

In other words, however "made-up" the 3nm marketing number may be, physics limits should still dictate a lower bound for it, and the OP seems to be wondering what that is.

There isn't an answer to that. We've already hit physical scaling limits for the old style (>40nm) of transistor manufacturing. Each successive generation since then has employed new tricks to improve performance, and each jump in performance is labeled with a smaller process node size number. This can keep going so long as there are more optimizations to be found. And since not all process optimizations involve shrinking dimensions, it's not necessarily the case that we can predict from physical principles when this will end.

For example, stacked chips are increasingly being used but are fundamentally limited by heat transport. Maybe when we get into sub-1nm "sizes" the process nodes will be defined by how well they transport heat out of volumetric chip designs? Or we'll switch to twisted graphene superconductors for certain components which increases efficiency without necessarily shrinking feature sizes. Etc.

I'm just throwing those possibilities out. The point is we can't predict when scaling will ultimately end.

That's still not a straightforward question to answer, because transistor shrinks aren't just about shrinking some dimensions while others stay at their limits. Transistor geometry has changed in more fundamental ways. Beyond ~28nm, the industry switched from planar transistors to FinFETs, so now instead of gate width we have an extra dimension and have to consider stuff like fin height and fin thickness and pitch. Starting around 3nm, we'll be seeing "gate all around" transistors—GAA FETs, in the form of nanowire, nanoribbon or nanosheets.

It depends on how one defines transistor, but if the definition of voltage controlled switch is sufficient then one atom will do.

https://en.wikipedia.org/wiki/Single-atom_transistor

This has nothing to do with the mass produced transistors (yet!) those are 10s of nm across even in 3 or 5nm.

So how big is a modern transistor? How close to together do the transistors get?

Does this mean there’s actually a lot more room to shrink things?

TSMC's 5nm 'N5' process -the highest density process currently shipping- has a raw transistor density of 173 million per millimeter^2. (https://en.wikipedia.org/wiki/5_nm_process)

If the transistors were laid out on a square grid (they aren't - it's rectangular), each square would be 76nm on a side. This area includes the transistor itself, the contact area (to connect the transistor to wires) and the required spacing to prevent the transistors from interfering with each other.

> "Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number."

That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent?

It seems like it's one thing to pick a specific dimension length to measure even if it's not proportional to all of the others, and another to just pick one that isn't represented at all.

3nm and 5nm are just marketing names it does not represent any geometry of the transistor. Probably the best analogy is 3nm would be the average length of the side of a pixel. One draws a transistor, or anything else, from many pixels.

The exact details are under NDA but to get a 'very' approximate idea of the scale of things one can look at the 5nm Wikipedia page.

They list the metal pitch as 30nm in TSMC's N5 node so in general two pieces of metal cannot be within 6 'pixels' of one another. One gets a rough guess on the distance between transistors by looking at the gate pitch (roughly 10 pixels in this case) but that measurement comes with a lot of caveats too.

Keep in mind this is when you're going out of your way to make something tiny but there are many good electrical engineering reasons to make the transistors larger still, and quite a lot of them are.

https://en.wikipedia.org/wiki/5_nm_process

Wikichip is also great. https://en.wikichip.org/wiki/5_nm_lithography_process

> That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent?

A progression over 5nm. That is all.

That was really instructive. Thank you for sharing.

I hate when people complain about how uninformed everyone is, but don't put in even the tiniest amount of effort to help people become more informed. At the very least, include a link.

It's not fair to blame people for not knowing that "3nm" does not mean "3nm". Knowledge about measurement units is more prevalent than knowledge about marketing practices of semiconductor companies. Blame those misleading practices instead.

Exactly as one vendors 7nm may well contain more atoms than another vendors 10nm node. Node numbers mean nothing beyond comparing against comparable node's.

Yes it's sad that node sizes are marketed in the same way the GHz race was at one stage and equally the disparity is greater when comparing nodes like for like.

Is there a dimension that can be used to compare across process tech since process node is now marketing and not gate length?

The narrowest dimension of a FinFET is roughly the process node size, within a small factor, so my comment applies. In fact, the first FinFETs were actually narrower than the node size when they were introduced.

It would be nice if we could standardize on some physical feature size that we would then call everything equally. It's silly to have a measurement system which is calibrated differently for what should be apples-to-apples comparisons. Imagine if some car manufacturers listed the length of their car from the rear bumper to the steering wheel and other measured their lengths from the rear bumper to the front bumper.

It may not be generally true but _it is_ true for the smallest possible feature so it's not entirely incorrect either.

This is unfortunately prevelant on most discussion forums. In many cases this correction is downvoted and buried deep.

and you're even getting downvoted for pointing it out...

The comment is not in the gray as I write this, but one tends to get better results generally by providing more information in a positive light, rather than simply saying that something is wrong without providing anything better.

For example, if the parent comment had said, "Yes, the control over small numbers of atoms is interesting. Although transistors are going to be much larger than that, it is cool that the shrinking feature size allows [making up a "fact" here for demonstration purposes] edges of transistors to be sharper and a little closer together, so yields are higher for a given transistor density," then it would be more useful and better received.

Also, remember "today's 10000": https://xkcd.com/1053/

But keep in mind, the parent poster likely didn't mean his words in a positive light. To portray them as such would be dishonest, which is unethical, confusing to all involved, and would lead to further confusion and incoherence as the conversation progressed.

and now I'm downvoted for pointing out that it's being pointed out... will it ever end?

(it was in the grey when I commented, but i upvoted it so I think that brought it back into the black)

It’s worth pointing out that these node names are only mildly related to feature size at this point.

They are more like minimum possible feature size, not average feature size. The real metrics you want to look at are things like transistor density, power density, power use, etc.

And even those things need to be assessed in the context of a specific design.

The real limits to performance aren't Moore's law: it's heat dissipation and the speed of light. We could do tons of high quality ML with 10nm+.

I'm not sure why I was downvoted, but my comment is technically correct (I work in ML and supercomputing; nearly all modern large ML and supercomputing devices are effectively a tradeoff between how much heat-producing CPU you can fit in a space, and how much latency-killing long cables you have.

See also: https://en.wikipedia.org/wiki/Limits_of_computation

For what an anecdote is worth, even back in the ‘90s my dad was telling me how the speed of light dictated the shape of supercomputers.

It was far worse then, as copper places serious upper limits on long-distance high-speed transport. Data transmission latency of copper tends to be 2X that of light (physical bounds, not empirically observed), and making very long cables with copper is impractical due to signal losses. Once long fiber was cheaply available people started to use that for the long links (imagine a toroidal mesh with wrap-around links- the wrap-around links are very long (100+m) and need to be fiber).

However, long fiber causes latency problems- those wrap around links will slow do any global reductions you need to do.

I can't help but imagine wormholes or FTL tech being first invented and used for longer distance interconnects in supercomputers. :-)

It's getting worse for AI chips and better for memory. GPU-type devices doing machine learning have all that compute silicon running flat out all the time, all emitting heat. Flash memory, at least so far, doesn't seem have the data rate to have a heat problem. At any one time, most of the device is inactive.

It's amazing that there are 2 terabyte USB sticks for US$40.

>It's amazing that there are 2 terabyte USB sticks for US$40

There aren't. There are scam products that claim to have 2 terabytes capacity though.

Not quite $40, but 2TB USB drives do exist. Who knows what you’d store on it though!

https://www.walmart.com/ip/Kingston-DataTraveler-Ultimate-GT...

We're not that far away from that point -- here's a 1 terabyte USB for $200: https://www.amazon.com/-/es/PNY-Elite-Flash-Speeds-P-FD1TBPR...

Bad link.

Here's the 2TB USB drive I was talking about.[1] It's on Amazon, so it's probably fake.

[1] https://www.amazon.com/jing-Compatible-Computer-High-Speed-D...

When it comes to flash memory, its best to avoid no-name brands and prices that seem too good to be true.

But considering we now have 1TB microSD cards, its definitely feasible to make a flash drive with such capacity

It is getting worse for Flash. There are consumer M.2 SSDs that have huge heatsinks and some even with fans!

Mark Cerny says this is a concern for PS5 which will have user expandable SSD storage. Unlike SATA drives, the M.2 standard doesn't define z-height, and the drives that meet the PS5 min spec are too thick right now.

The main problem there is the SSD controller interfacing between the flash memory and the CPU. Right now, the only SSD controller that supports PCIe gen4 speeds and is small enough to fit on a M.2 card is a controller made on TSMC's 28nm process. Everybody else in the industry decided to move to TSMC's 16/12nm processes before trying to ship a high-performance PCIe gen4 SSD controller. Doing really advanced error correction at 5+ GB/s takes some juice, so SSD controllers have to follow in the wake of CPUs and smartphone SoCs by moving to smaller but more expensive (at least up front) process nodes.

It's not going to happen any time soon, but I'm looking forward to "computronium" as described in sci-fi - a computing substrate optimized at the molecular level to the point that the performance becomes the function of its volume.

I wonder if we can go to even higher density. From entropy constraints, computing performance asymptotically scales with surface area [0,1]. The general bound is Bekenstein bound[2]

[0] https://en.wikipedia.org/wiki/Black_hole_thermodynamics

[1] https://en.wikipedia.org/wiki/Holographic_principle

[2] https://en.wikipedia.org/wiki/Bekenstein_bound

The bound exists, but it's so many orders of magnitude out that for all practical purposes we don't need to worry about it.

Of course, however, heat dissipation presents similar challenges.

It'll be interesting to see how/if quantum effects will be used in future computing tech (well aside from the whole quantum bangaps in semi-conductors). Effects like thermal super-conductors could enable much higher heat in a given area, perhaps built with quantum dots on semiconductors (IIRC, I thought some researchers tried that).

I guess if we hit the edge of feature density, we might start building things out of 3d FPGA type designs of homogeneous modules but because of heat, the capacity of such a design is ultimately going to be limited by its surface area, not its volume, no?

My CPU is a sphere!

Here's a helpful recent read on what the metrics mean and what semis are trying to replace them with: https://www.gwern.net/docs/cs/2020-moore.pdf

Indeed. I know there was a working 1nm node transistor out of Berkeley a couple years ago, but as far as I know that's pretty close to the limit. I'm really curious what will come after we hit that in production in ~10? years.

Single-atom transistors are a thing. I can’t even begin to guess how difficult anything like that will be to mass-produce.

https://en.wikipedia.org/wiki/Single-atom_transistor

Can you link to that?

Sure thing: https://newscenter.lbl.gov/2016/10/06/smallest-transistor-1-...

Thanks!

Intel has a roadmap to 1.4nm

There are plenty of areas for improvement beyond pure transistor size:

- density

- heat

- resistance