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Re:TSMC and Graphcore Prepare for AI Acceleration on 3nm by egsmi on Thursday August 27, 2020 @03:55PM (#24297918)
Nice explanation. One can see an example of the scalable CMOS design rules on slides 10 and 11 of this deck.

https://inst.eecs.berkeley.edu/~cs250/fa09/lectures/lec01.pd...

(To the casual reader: Note how the dimensions all have no unit. There are measured in L as indicated by the parent.)

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