There isn't an answer to that. We've already hit physical scaling limits for the old style (>40nm) of transistor manufacturing. Each successive generation since then has employed new tricks to improve performance, and each jump in performance is labeled with a smaller process node size number. This can keep going so long as there are more optimizations to be found. And since not all process optimizations involve shrinking dimensions, it's not necessarily the case that we can predict from physical principles when this will end.

For example, stacked chips are increasingly being used but are fundamentally limited by heat transport. Maybe when we get into sub-1nm "sizes" the process nodes will be defined by how well they transport heat out of volumetric chip designs? Or we'll switch to twisted graphene superconductors for certain components which increases efficiency without necessarily shrinking feature sizes. Etc.

I'm just throwing those possibilities out. The point is we can't predict when scaling will ultimately end.

That's still not a straightforward question to answer, because transistor shrinks aren't just about shrinking some dimensions while others stay at their limits. Transistor geometry has changed in more fundamental ways. Beyond ~28nm, the industry switched from planar transistors to FinFETs, so now instead of gate width we have an extra dimension and have to consider stuff like fin height and fin thickness and pitch. Starting around 3nm, we'll be seeing "gate all around" transistors—GAA FETs, in the form of nanowire, nanoribbon or nanosheets.

It depends on how one defines transistor, but if the definition of voltage controlled switch is sufficient then one atom will do.

https://en.wikipedia.org/wiki/Single-atom_transistor

This has nothing to do with the mass produced transistors (yet!) those are 10s of nm across even in 3 or 5nm.