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Re:TSMC and Graphcore Prepare for AI Acceleration on 3nm by fossuser on Thursday August 27, 2020 @03:18PM (#24297523)
> "Regardless, as stated in the parent, there is no single dimension of any recent process that corresponds to the '3nm' number."

That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent?

It seems like it's one thing to pick a specific dimension length to measure even if it's not proportional to all of the others, and another to just pick one that isn't represented at all.

Re:TSMC and Graphcore Prepare for AI Acceleration on 3nm by egsmi on Thursday August 27, 2020 @03:32PM (#24297673)
3nm and 5nm are just marketing names it does not represent any geometry of the transistor. Probably the best analogy is 3nm would be the average length of the side of a pixel. One draws a transistor, or anything else, from many pixels.

The exact details are under NDA but to get a 'very' approximate idea of the scale of things one can look at the 5nm Wikipedia page.

They list the metal pitch as 30nm in TSMC's N5 node so in general two pieces of metal cannot be within 6 'pixels' of one another. One gets a rough guess on the distance between transistors by looking at the gate pitch (roughly 10 pixels in this case) but that measurement comes with a lot of caveats too.

Keep in mind this is when you're going out of your way to make something tiny but there are many good electrical engineering reasons to make the transistors larger still, and quite a lot of them are.

https://en.wikipedia.org/wiki/5_nm_process

Re:TSMC and Graphcore Prepare for AI Acceleration on 3nm by fomine3 on Friday August 28, 2020 @02:57AM (#24302088)
Re:TSMC and Graphcore Prepare for AI Acceleration on 3nm by garmaine on Thursday August 27, 2020 @03:39PM (#24297745)
> That's interesting - are they just entirely making that up then? What's the 3nm supposed to represent?

A progression over 5nm. That is all.