The main problem there is the SSD controller interfacing between the flash memory and the CPU. Right now, the only SSD controller that supports PCIe gen4 speeds and is small enough to fit on a M.2 card is a controller made on TSMC's 28nm process. Everybody else in the industry decided to move to TSMC's 16/12nm processes before trying to ship a high-performance PCIe gen4 SSD controller. Doing really advanced error correction at 5+ GB/s takes some juice, so SSD controllers have to follow in the wake of CPUs and smartphone SoCs by moving to smaller but more expensive (at least up front) process nodes.