This post is incredibly frustrating to read.

> "companies A, B, C, and D are producing w, x, y, and z nm transisters"

> "you have to ignore what nm they used, because actually w nm = x/2 nm"

> continues to use company-specific nm instead of comparable units

> reminds you again that the numbers are not comparable

> continues to use company-specific nm instead of comparable units

> “We’ve also packed them closer together to improve transistor density,” said Kaizad Mistry

Yes, that is what density means. Very good!

> "And forming the gate itself is also challenging. “Cycle times are increasing for this step, driven by the complexity of the stack,” said Mohith Verghese, director of global product marketing at ASM International. “The metal gate stack is also getting very complicated."

Oh, it's getting challenging, complex, AND complicated!

> There are several layers in the metal stack.

I think you just told me that a stack of something has several layers. Also that the metal gate stack is metal.

> And issues, such as... all add to increased cycle time.”

So cycle times are increasing because issues lead to increased cycle time?

...

gah. I want to finish this, but it's just so hard to read a pile, with several layers of course, of redundant PR snippets.

...

> performance become limited, mainly by the contact and back-end-of-line, because those become the bottleneck.”

FFFFFFUUUUU

Christ on a cracker, get an editor. Oh...you ARE the editor. <cries>

In fairness, this is a horrifically complex subject. Pretty much every point you mention is a rabbit hole that you can spend ages exploring.

e.g. the metal stack: One would like to connect transistors together. Copper is lower resistance than doped silicon, so we'd prefer to use copper. But there's a catch: copper diffuses into silicon. That is, if you attempt to directly plate copper onto silicon, some of the copper diffuses into the silicon crystal mucking up all the careful doping of the silicon we just did.

So we put down a barrier layer first: We first coat the silicon with tantalum nitride which has significantly lower diffusion rates into silicon. And then we put copper on. No! Wait! We can't put copper directly onto tantalum nitride for <complex reasons this margin is too small to contain>. So we put tantalum metal onto the nitride,and then we put copper onto that metal.

This is the sort of thing that referred to as a metal stack. I've hand-waved like crazy here. The actual metal stacks are way more complex than this.

The article alludes to some of the recent challenges: The tantalum nitride barrier layer is too thick so there's a move to replacing it with a cobalt based stack, or maybe even a manganese/ruthenium based stack.

The author had a pretty tough job in trying to explain some of what's going on to a lay audience and (likely) do it inside a word limit. We can argue about successful it was on the margins, but personally I'm still very appreciative that they tried :)

> The author had a pretty tough job in trying to explain some of what's going on to a lay audience and (likely) do it inside a word limit.

The author would have had an easier time staying within a word limit if they didn't say the same thing multiple times in a row everywhere. Honestly, it looks like they had exactly the opposite problem of what you're suggesting and were trying to fill more space without understanding the subject. Much of the article is just parroting redundant PR soundbites.

It's a terrible article on an important subject.

He completely ignores the extreme ultraviolet "light source" problem. As the features get smaller, light wavelengths are too big, and higher frequency light has to be used to get the wavelength down. Current technologies use ultraviolet light. The next step down in size is "extreme ultraviolet", which is actually soft X-rays. The "light source" can be either a synchrotron or an an incredibly expensive kludge where droplets of tin are vaporized by lasers.[1] 30KW of laser power goes in to produce maybe 100 watts of useful illumination. Two floors, tons of equipment. All this just to expose a photosensitive resist on the wafer.

At 14nm, the UV light source is a modest device. Getting to 7nm is enormously more complicated. 7nm may not be cheaper per gate.

[1] https://www.youtube.com/watch?v=8xJEs3a-1QU

There's lots of fun here!

> It will cost $271 million to design a 7nm chip, according to Gartner.

Not a million more, not a million less.

> As the size shrinks, less and less area and volume are available

Wait, are you sure?

Unclear. Sometimes a smaller size like 7nm is actually 10nm. To summarize 10 > 7 BUT 7 = 10.

> Cost, of course, is key because only a select group of foundry customers with deep pockets can afford 10nm and 7nm

Really? I wouldn't have known that only people with more money can spend more money

This is vastly overstated by the way. Maybe to design a de-novo X86 competitor chip. ARM's entire operating expenses in the last 12 months are about $700mm, for every single bit of their company. No way that a single 7nm chip costs $270mm for design.

Design is not the same as tape-out. ARM designs the logical structure of its chips (the VHDL or Verilog). They then license that design to customers (such as Apple, Samsung), who customise it.

The tape-out is completely separate from that. You need to do the physical layout and produce a set of lithographic masks that are incredibly expensive. Back in 2000, a set of masks for the most advanced technology at the time was already in the millions of dollars. Things have gotten ridiculously more complex since then.

> Moore's law might be slowing, but the challenges are accelerating

Uh, ya. They are inversely correlated. The harder it is to do something the longer it takes.

All the node names are effectively useless now. A good rule of thumb is that TSMC 7nm ~= Intel 10nm and they're shipping at approximately the same time.

And last time I checked into it, neither has much to do with 7 or 10 nanometers. The 'feature sizes' of old are not actually on that scale, rather it's more a measure (read: marketing speak) of resolution than of feature size at this point? I still can't get good answers. As a biologist used to working with objects that actually do have features on the order of 0.1nm, and volumes with less than <5nm per side, I'm trying to figure out just how big these transistors really are to fit into my existing mental models. At what point do the transistors actually have to start dealing with (can they deal with) quantum/thermal/structural effects of being so small.

> At what point do the transistors actually have to start dealing with (can they deal with) quantum/thermal/structural effects of being so small.

I think that was about a decade ago. These things simply cannot work if they ignore the quantum effects at their size.

I guess the better way to ask is when do those effects dominate rather than merely effect. At what point do structure and feature type need to actually change?

I'm assuming Samsung and TSMC follow the same convention? So what does Samsung's 14nm chip map to in Intel's dimensions?

It's exciting to see such an incredible rate of advancement; I can't wait to see what transistors at 7nm and less will make possible. I can still remember when these same components were measured in millimeters.

Chips that are just like the ones we have now but 30% cheaper? I don't see how this is going to open up whole new technologies that weren't possible at 10/15nm.

Technology getting cheaper allows to apply this technology to problems where it was not economically sustainable previously.

IMO it's a good thing.

Maybe not, but better battery life and eventually cheaper hardware on mobile and low power devices, expanding the range of usefulness in the developing world especially, is no small thing.

One of the biggest advancements due to this kind of tech has actually been throughput for radios. By using more sophisticated / denser encodings, we can scale the same 4G tech to even higher speeds. Think 1gbit/s speeds for mid-market phones. This is effectively enabled due to the smaller node sizes also being more power efficient, which is required for mobile phones.

The advances are less in your face, but still there.

Yes, we need technology that increases CPU clock speed above the current plateau.

Why do you think we need to increase individual clock speeds past their current limits?

due to Amdahl's law, it's always better to have a single faster processor than multiple slower ones.

...but do we really need faster processors? i don't know, but i'd like to have one :)

It's easy to think we need faster processors when the architectures we use, both software and hardware, are incredibly inefficient.

Any modern processor is much faster than the RAM its programs and data live on, hence the multiple levels of cache inside them. Multi-cores add the complexity of keeping the memory consistent. Multiple threads per core put additional pressure on caches while our OSs assume all processors see a unique and consistent memory image (which requires keeping caches consistent across cores). Our most common software doesn't run on GPUs before extensive changes. Only mobile platforms are exploring asymmetric multiprocessing with a single ISA now.

I don't think we need faster single-thread performance. What I think we need is to adapt our software, which is designed to run on ridiculously fast copies of ancient personal computers, to run on computers that instead of mimicking a successful product of the 80s resemble more what we can do now. We need software that exploits the SIMD units (predicate bits that prevent branches are your friends there), that runs well in multiple cores and OSs that can deal with memory inconsistency between cores (maybe using write-through instructions for shared data and write-back for process-local stuff). We need software that doesn't need complicated instruction reordering or speculative execution.

> due to Amdahl's law, it's always better to have a single faster processor than multiple slower ones

This is not what Amdahl's law says. Amdahl's law gives you a theoretical maximum speedup given a program with a sequential component and a given number of processors. So as long as that speedup is higher than your faster processor is faster then it does make sense to have multiple slower processors than one faster one.

There are many products that don't see the light of day because they can't meet their COGS target. Cutting a huge chunk by 30% could open up a bunch of amazing functionality.

I think the point is that the rate of advancement has already slowed (18mo=>3yr) and is slowing even further (5nm by 2025). The treadmill Moore's law is basically over. There will be significant advancements (AllAroundGate, Wafer Stacking), and we might even see a speed increase again, but the steps are more orthogonal and less all improving. The last thing to keep improving is $/transistor, while MHz and power long since (2005=>2010) stopped getting better with each node. However, if the CFOs ever figure out that the return doesn't meet investment ... that will be the end (at least in the west).

I would say the rate of advancement is kind of plateauing. From the p4 to athlon 64 to c2d the gains were quite amazing. I guess in mobile you still see advancement, but do you really notice the difference between a snapdragon 801,820,835?

It is hard (read expensive) to go under 14nm.

Sophie Wilson talks about it much better then i could. https://www.youtube.com/watch?v=_9mzmvhwMqw

My understanding is that the actual pitch is not getting considerably smaller, despite the (still fairly large) changes in quoted node size.

Also the cost per wafer for TSMC 20nm is still the same as when TSMC 40nm was introduced, the latter today is about half as much money, AFAIK. 16nm is about half way between the introductory price of 20nm.

The transistors are getting slightly smaller, but the cost per transistor seems to be staying the same or increasing; Moore's law really died like... a decade ago.

These days you see us coming to terms with it. For years we've been telling people that computing resources are abundant and they needn't worry about memory or CPU time because their application will double in speed in a year. This is probably why most websites are awful these days, and take more time than ever to do things they did nearly 20 years ago in half the time.

Once you get down to 7nm don't quantum effects become harder to deal with? Don't know much about chip design but I seem to remember as things get really small it gets harder to isolate components.

Yes, quantum tunneling is a real problem and has been an increasingly dangerous issue as the nodes shrink. Three interesting proposals to try and mitigate the issue are:

1. TFETs, aka Tunneling FETs, harness the leakage current itself to drive the transistor.

2. Quantum well FinFETs, use the quantum well to constrain the electron movement and circumvent the problem.

3. This is more of a stopgap measure, but the usage of SiGe FinFETs with FD-SOI.

You already had quantum effects at 14,20,32nm etc.

Hence, engineering.

Also apparently GloFo is developing its own 7nm process (its ancestry was at IBM before GloFo bought them iirc) but not licensing Samsung like with 14nm.