What will be cost estimate for a PCI-e board ? Chip ? if this thing touches consumer hands.

Are you planning any production samples for research / universities / DARPA ?

The chip is about the same size as the Apple A10, so in terms of silicon area it's in the consumer domain, but price will only come down to consumer levels if shipments get into millions of units. Big companies take a leap of faith and build a product hoping that the market will get there. Small companies get one shot at that. With University volumes and shuttles, we are talking 100x costs. So the $300 GPU PICe type boards become $10K-$30K with NRE and small scale productio folded in.

You should look into alternative financing methods.

How long is the period from needing the cash to pay for production to availability in retail, roughly?

If it's all about volume, accumulating orders over a long period using some non-reversible payment method could, perhaps, get you into millions of units. It's all about how long people are willing to wait in order to save on per-chip unit costs.

What type and size memory can the Epiphany-V support?

Also congrats! This is brilliant engineering to get a chip like this into production silicon as a small team.

How much did the prototype MPW(?) silicon cost?

Up to 1 petabyte supported theoretically through FPGA interfaces.

We can't disclose MPW costs. Chip was funded by DARPA. For standard MPW costs, check with MOSIS.

https://www.mosis.com/

I had a friend who mentioned that it was very difficult to get the 64-cores Parallellas with fully-functional Epiphany-IV chips. Are these yield problems going to continue with Epiphany-V or can we expect a full 1024 functional cores per chip?

It would be a BIG mistake to assume 1024 working cores. If you want to scale your software you should take a look Google/Erlang and others. Not reasonable to demand perfection at 16nm and below...

Not saying we won't have chips with all cores working, just saying you shouldn't count on it.

So what can we count on?

In a tile based CPU error topology matters. A string of broken cores or a broken core at the edges is likely worse than a broken core with all 4 (or 8?) neighbors working.

Impossible to characterize without high volume silicon or accurate yield models. We can say that historically, most failures are in SRAM cells and they are limited to a few bits (core still works!) and that in general only one out of N cores will fail. For arguments sake, let's assume the while network always works, but 1 CPU may be broken. (this is what needs to be confirmed later). Does that help?

Yes, that helps.

It might be easier to work around broken SRAM bits than just skipping a whole core.

That way you could always have same pipeline layout and not need to compute it dynamically.

You refer to the per-CPU SRAM as "memory" rather than "cache". It's just addressable local memory?

How many DRAM ports?

Yes, you can call it scratchpad or sram. The point is that there is no hardware caching. The local SRAM is split into 4 separate banks so it is "effectively" 4 ported. DRAM controllers is up to the system designer. This is handled by the FPGA. (like previous epiphany chips).

What are the chances of seeing a new Parallella SBC with an Epiphany-V coprocessor coupled with a RISC-V main processor?

Not going to happen in the near term. There is no way to meet the price point needed to compete in the low cost SBC market with the Epiphany-V. Believe it or not, the $99 Parallella was priced too high to reach mass adoption.

How about a evaluation board which plugs into the mezzanine connectors of the ZC706 evaluation kit? Something similar to the AD9361 FMCOMMS3/5 [1]

Also: any more information on the ISA extensions for communications/deep learning?

[1] https://wiki.analog.com/resources/eval/user-guides/ad-fmcomm...

Sure, there will be evaluation boards, they just won't be generally available at digikey and won't cost $99. More information about custom ISA will be disclosed once we have silicon back.

Having seen that the $99 price point was too high, is one of your goals still "supercomputing for everyone"? Or has that dream been dashed?

Well, the Parallella has shipped to over 10,000 people and it still selling at Amazon an DK, so no the dream is not dashed in any way. The number of publications and frameworks around Parallella is growing every month...

No reason to drive a 1024 core chip to the broad market when most applications aren't ready to use 16 cores. With this chip we focus on customers and aprtners who have proven that they have mastered the 16-core platform.

>No reason to drive a 1024 core chip to the broad market when most applications aren't ready to use 16 cores.

Yet magically they have no problem taking advantage of massively parallel GPUs...

Most applications don't use 16 CPU cores because they don't need them.

I think you're underestimating the requirements and mastery of cloud companies. Something like an Amazon lambda could virtualize 4 cores per instance and host 256 lambda execution units on a single chip. The use cases are endless

Unless the architecture has changed drastically from the earlier Epiphany, they can't be virtualised like that, and each core are way too slow to be suitable for lambda except for software written specifically to take advantage of the parallelism of the architecture.

You still need to recompile code for the new architecture, and taking full advantage of it wisely is not easy... but may be worth it in many use cases. Part of the problem is that it's not 100% clear which use cases these are and how to market it. Probably unit calculation per watt is the most likely performance advantage, but it's still amazingly hard to sell people on that sometimes

Some parallel algorithms will scale to bigger (more parallel) chips the way binary programs got more performance with clock higher frequencies. That's the holy grail..

Congrats again on getting amazing amount done on budget. The part that jumped out more than usual was you soloing it to stay within budget. Pretty impressive. How did you handle the extensive validation/verification that normally takes a whole team on ASIC's? Does your method have a correct-by-construction aspect and/or automate most of the testing or formal stuff?

Modern SOCs might have 100 complex blocks. We had 3 simple RTL blocks (9 hard macros). Top level communication approach was "correct by construction". Nothing is for free.

That makes sense. Appreciate the explanation.

4100 hours in about ten months (according to the PDF). Did you really put in 100 hour work weeks?

Hours were over a 12 month period, but yes...the pace was relentless. All ambitious projects, including many kickstarer projects get done because creators end up working for free for essentially thousands of hours. In this case, we were on a fixed cost budget so those hours were "my problem".

#1 on HackerNews is worth it. Congratulations, man!

Are your competitors GPUs and or Xeon Phi? What is programming on this chip and how is the instruction set designed?

Documents:

http://adapteva.com/docs/epiphany_arch_refcard.pdf http://adapteva.com/docs/epiphany_arch_ref.pdf

Not competitors yet. They have awesome silicon in the field, we just taped out...

Vim or Emacs? :trollface:

But seriously, I'm tremendously curious about the use for this with video processing. Has there been any good benchmarks with that?

Emacs!

Here's one from ARL:

http://www.ieee-hpec.org/2015/finalpapers_site/17_87-Impleme...

Emacs? Ahem. I would like to return the parallella I purchased in the kickstarter campaign...

Just kidding. Nobody's perfect. :)

Awesome to see the 1024 cpu epiphany taped out! Congratulations! Any plan to put these into a card computer for easy programming and evaluation? EDIT: nevermind on the question, I see the response below.

Would like to say that your kickstarter was one of the best communicated most smoothly run kickstarter campaigns that I have ever backed.

:-) Thanks for making me laugh :-)

Hopefully you guys have ECC on your 64MB of SRAM, otherwise the meant time to bit flip due to Single Event Upset (SEU) is around 400 days ( based on 200 Fit/Mb/Billion Hours from previous experience ).

No ECC on chip, but we do have column redundancy. We are pushing the envelope in terms of SEUs, making an assumption that the right programming model and run time will be able to compensate for high soft error rates. It's a contentious point, but basically our thesis is that with 1024 cores on a single chip, cores are "free" and it "should" be possible to avoid putting down very expensive ECC circuits on every memory bank (x4096). Some of our customers don't notice all bit flips because they have things like Turbo/Viterbi ..channels aren't perfect...

This is a bit of a dumb question; when do you feel your site is going to be back up? I would actually rather like to buy a Parallella...

I know...it's painful, we honestly weren't expecting this.

Here are direct links if you are in a rush:

Amazon: https://www.amazon.com/Adapteva/b/ref=bl_dp_s_web_9360745011...

Digikey:

http://www.digikey.com/en/product-highlight/a/adapteva/paral...

Cool, stuff for sure.

I didn't see it addressed in the paper, how does this compare WRT discrete DSP chips? Are you targeting ease of programming instead of raw FMAD/etc?

In modern DSP chips programmers have to contend with: VLIW, SIMD, pipelines, caches, and multicore.

In Epiphany, the programmers are challenged by the manycore and an SRAM size cliff (so 0 or 1 in terms of pain).

It depends...but I personally prefer having one big dragon to slay rather than 10 little ones.

Thanks, sounds like lots of parallels(har har) to the SPUs on the PS3 which got a bad rep but I thought where great if you went in with the right approach.

I see that there is a llvm backend at https://github.com/adapteva/epiphany-llvm, but it hasn't been updated in a while. Are there any plans on upstreaming/contributing and maintaining a backend for llvm?

We are quite happy with our GCC port so LLVM hasn't been a priority. If anyone wants to take over the port, please do! We could give financial assistance for getting it completed, but the budget would be modest.

What is your software story for this thing?

Are you upstreaming qemu, uboot, Linux, GCC, GDB etc changes?

Will we see a Debian port for this?

For Epiphany: GCC upstream already, working on GDB upstreaming. THere is no linux, qemu,uboot

For Parallella: Linux upstream, uboot might be as well? Runs Debian, Ubuntu, etc

https://github.com/adapteva

So what do you run on Epiphany if there is no Linux?

First of all, congrats, this is very impressive. Second of all, I've been thinking a lot about how proprietary GPU computation and especially VR is these days. Any interest or plans for the future in specialized hardware development for VR?

When are dev-boards coming out?

Can it run off Power over Ethernet? That would be interesting.

Sure...but probably not with all cores running full throttle. Would need to build an appropriate board.