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A comment on Epiphany-V: A 1024-core 64-bit RISC processor. Parent comment

Re:Epiphany-V: A 1024-core 64-bit RISC processor by adapteva on Thursday October 06, 2016 @06:10PM (#12656559)
Modern SOCs might have 100 complex blocks. We had 3 simple RTL blocks (9 hard macros). Top level communication approach was "correct by construction". Nothing is for free.
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Re:Epiphany-V: A 1024-core 64-bit RISC processor by nickpsecurity on Friday October 07, 2016 @12:01AM (#12658068)
That makes sense. Appreciate the explanation.
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