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Re:Epiphany-V: A 1024-core 64-bit RISC processor by nickpsecurity on Wednesday October 05, 2016 @02:19PM (#12646371)
Congrats again on getting amazing amount done on budget. The part that jumped out more than usual was you soloing it to stay within budget. Pretty impressive. How did you handle the extensive validation/verification that normally takes a whole team on ASIC's? Does your method have a correct-by-construction aspect and/or automate most of the testing or formal stuff?
Re:Epiphany-V: A 1024-core 64-bit RISC processor by adapteva on Thursday October 06, 2016 @06:10PM (#12656559)
Modern SOCs might have 100 complex blocks. We had 3 simple RTL blocks (9 hard macros). Top level communication approach was "correct by construction". Nothing is for free.
Re:Epiphany-V: A 1024-core 64-bit RISC processor by nickpsecurity on Friday October 07, 2016 @12:01AM (#12658068)
That makes sense. Appreciate the explanation.