adapteva

Synopsys has a $100B market cap. Why would Alphabet buy them and open source the IP? That makes no economic sense.

The open source tools are great, I use them every day...however, they are light years away from being feature complete for doing a complex products (synthesis qor, multi clock cts, timing driven placement, upf support, statistical timing, too many features to count)...it's death by a thousand paper cuts. Once all those features have been implemented, the next barrier is to get first class status with foundries who ship the EDA development. Currently most only ship enablement for synopsys and cadedence.

Does anyone have the backstory on this?

Exactly why we zero asic is making Platypus devices open bitstream and all tooling foss from day one...to protect the world against future evil/dumb version of ourselves.

https://www.zeroasic.com/platypus https://www.zeroasic.com/projects/wildebeest https://www.zeroasic.com/projects/logik

Of course we don't have silicon yet...so nobody here cares. I think a lot of people forget that Xilinx spent $10B+ develop their awesome devices. I figure we can do it with 1/10th of that.;-)

Thank you, comment made my day:-)

Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86.

Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.

We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)

Documentation can be found in two places. What else do you need to know?

https://github.com/siliconcompiler/logiklib/tree/main/logikl...

https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC.

https://github.com/zeroasiccorp/wildebeest

No strings common share purchase means cash in hand, which implies Intel can spend it on any operational cost, including buying billions in TSMC wafers (which they already do).

Any strings attached? If not, ironically a big chunk of those US tax payer dollars will likely end up in Taiwan/TSMC.

Weird title, makes it seem like a reveleation. There have been numerous Viking treasures discovered in Sweden with traces from the the Islamic world and it's well known that they were all over England as well.

https://en.wikipedia.org/wiki/Spillings_Hoard

The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000).

We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...

First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic.

The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the first standard is to be the lowest common denominator of FPGAs that anyone can implement, else the threshold is too high. Kind of like RV32I.

So RL does a few % better job at "learning" the correct combo of thousands of settings needed for black box EDA PNR. Not surprising. Exciting from a research perspective perhaps, but that doesn't crack the top 10 most important challenges for chip design.

Oh no, we have lost another giant! Very few people in the world know the gratitude she is owed. I doubt Nvidia and the other fabless companies would exist without her contribution. I met her through DARPA in 2018 [ref] and I later reached out for advice when I started a company in 2020. She was kind and generous with her time in all of our interactions. Beyond her technical prowess, she really understood people. The community/collabroation aprpach she used to launch the VLSI revolution in the 1970's are worth studying.

RIP

[ref] https://youtu.be/W_cB8VYunY8?si=9M9QVmBipbKUXxMR&t=1414

Yup, got an cold email from them. Marked it as spam and never heard from them again...

Yes, that's a great idea, but none of the projects you mentioned are ready for production. Who will find the building of these products?

Yes

Makefiles can work for simple builds. Logik being Python based can do so much more: automated metrics gathering, conditional flows, parallel execution, error handling, dependency management

Haha, cool to see this on HN.:-)

Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn't really been done before.