Re:Epiphany-V: A 1024-core 64-bit RISC processor
by adapteva on Wednesday October 05, 2016 @07:59PM
(#12649040)
In modern DSP chips programmers have to contend with: VLIW, SIMD, pipelines, caches, and multicore.
In Epiphany, the programmers are challenged by the manycore and an SRAM size cliff (so 0 or 1 in terms of pain).
It depends...but I personally prefer having one big dragon to slay rather than 10 little ones.
I didn't see it addressed in the paper, how does this compare WRT discrete DSP chips? Are you targeting ease of programming instead of raw FMAD/etc?