RDIMMs are implicitly ECC.

There's UDIMMs (typical RAM from desktops), and then RDIMMs (Registered), and LRDIMMs (Load-Reduced DIMM).

Because RDIMMs and LRDIMMs are only used on servers, they're all ECC / Error Correction just implicitly. At least, I've never seen an RDIMM or LRDIMM missing ECC.

You used to see it in workstation builds, although I can't remember the last time I saw that configuration lol. It's certainly not something you'd see often even then.

The workstation market is split between platforms using RDIMMs and UDIMMs (and has been for a very long time), but the RDIMMs still always have ECC and the UDIMMs for systems branded as workstations almost always have ECC.

My threadripper pro workstation (Lenovo p620) uses RDIMMs. So at least one manufacturer still has them in production.

RDIMM

Also if you look at the picture, there's five columns of packages per channel.

All DDR5 has ECC built into the modules.

I thought that was per chip ECC not per module? (May be wrong on that)

You’re right, and I was being imprecise. I was trying to convey that the functionality was entirely contained within the chip/module unlike traditional ECC which passes the parity data back to the CPU.

The parent said the chances of a single bit flipping are too high without it, they are, which is why it’s in the spec :) These densities wouldn’t be possible without it.

There are DDR5 modules with traditional ECC though, which the parent poster presumably meant.

All DDR5 has ECC built into the modules for it to reach parity DDR4.

ECC memory modules are better because they can fix and report errors, the base DDR5 DIMM will hand you a piece of memory with multi-bit corruptions that it couldn't fix. The ECC DIMM will fix larger errors and tell you about each detected corruption.

But there are ECC DIMMs with even better ECC. DDR5 moved the DIMMs from one 64-bit channel to two 32-bit channels. ECC DDR4 you'd protect 8 memory dies with 1 memory die holding the ECC, your computer will identify it as 72-bit memory. ECC DDR5 you protect the 4 memory dies in the half channel with a dedicated 5th die on each channel. Some ECC DDR5 will have 80-bit ECC, some will have 72-bit ECC. You want the 80-bit ECC because it stores 8 more bits of ECC for your memory controller to correct errors.

Micron isn't known for making 80-bit DIMMs.

I would add that "has ECC" is even more complicated than you've implied here. There are many ways to detect and correct DRAM errors, and with the memory controllers moved into the CPU the features you get depend on your CPU vendor, firmware, and operating system. To get the most out of a current Xeon SP, for example, you want 10x4 DDR5, that provides 8 code bits with each 32 bits of data. All of the players in the business have patents on some part of ECC, so you get a grab bag of techniques on different platforms.

ECC is not complicated. Manufacturers pretend it's complicated in order to sell you inferior product at inflated prices.

It's really simple: just demand SECDED.

That's all you need to know, one acronym, SECDED.

https://cr.yp.to/hardware/ecc.html

Single Error Correction, Double Error Detection.

BTW, this sort of ECC fraud has been going on since the 1990's at least. It isn't going to just go away. Learn what SECDED is and demand it.

It really isn't that simple. For example, the distinction you're ignoring from the comments you replied to is the question of correcting a single error among how many bits: one bit error across the full 64-bit width of a DIMM, or one bit error per each 32-bit sub-channel now that DDR5 has split the DIMM in a way that previous desktop memory standards don't.

Where a non-ECC DIMM is usually 8 DRAM chips (64 bits) and in DDR4 or earlier and an ECC DIMM would be 9 DRAM chips (72 bits), now with DDR5 can have either 9 DRAM chips or 10 DRAM chips (80 bits).

It's really that simple.

> the complexities of having ECC protection only on the link

That's not SECDED, since it can't correct a bitflip that occurs somewhere other than on the link, nor can it detect a double bitflip in those situations.

SECDED. Just ask for SECDED.

Even the Linux kernel knows about this:

   # cat /sys/devices/system/edac/mc/mc1/csrow3/edac_mode
   SECDED

SECDED. Just ask for SECDED.

> That's not SECDED, since it can't correct a bitflip that occurs somewhere other than on the link

You're just making up arbitrary rules. The term SECDED does not incorporate any guarantees about which part of a system it applies to. It's just a mathematical statement about the strength of the ECC in use plus the implication that detectable but uncorrectable errors are reported.

What you're looking for requires more words to fully specify, probably including the term "end to end".

Your mantra is sort of hilarious because with current technology SECDEC is the worst ECC you can buy. If that's what you are getting on a DDR5 server today, the most likely reason is your integrator has made a mistake.

There seems to be some confusion in the replies to your post.

What I’ve read is that DDR5 has “on-die ECC” which means that the module itself handles the error correction, but then it can not handle errors that happen in transit to the CPU as full ECC can.

There are DDR5 full-ECC modules that would be real equivalents to DDR4 ECC.

> When the latest version of DDR memory – DDR5 – was introduced in 2020, marketing campaigns got one important fact wrong. DDR5 UDIMM, the regular desktop RAM we’re all familiar with, was touted as having “built-in” Error Correcting Code (ECC). Not true. What it has is built-in data checking, which is a very different feature that shouldn’t be confused with traditional ECC. For that, your customers will need DDR5 ECC UDIMM memory.

— Intel, “Error Correcting Code (ECC) vs. Built-in Data Checking”: https://www.intel.com/content/www/us/en/content-details/7549...

Additionally, on-die ECC isn't unique to DDR5; it's a necessity for any DRAM built on the most recent high-density fab processes. It was used for at least some LPDDR4 memories, and probably most or all LPDDR5.

Can't wait to see another round of rowhammer papers trashing these things. XD

Row and col lines are so close nowadays; you are fighting physics... Older processes didn't have this problem due to row isolation.

It's not the selection lines, up on higher metal layers. It's the actual memory cells themselves being too close together on the substrate.

That's mostly because otherwise they wouldn't be reliable enough to use.