It really isn't that simple. For example, the distinction you're ignoring from the comments you replied to is the question of correcting a single error among how many bits: one bit error across the full 64-bit width of a DIMM, or one bit error per each 32-bit sub-channel now that DDR5 has split the DIMM in a way that previous desktop memory standards don't.

Where a non-ECC DIMM is usually 8 DRAM chips (64 bits) and in DDR4 or earlier and an ECC DIMM would be 9 DRAM chips (72 bits), now with DDR5 can have either 9 DRAM chips or 10 DRAM chips (80 bits).

It's really that simple.

> the complexities of having ECC protection only on the link

That's not SECDED, since it can't correct a bitflip that occurs somewhere other than on the link, nor can it detect a double bitflip in those situations.

SECDED. Just ask for SECDED.

Even the Linux kernel knows about this:

   # cat /sys/devices/system/edac/mc/mc1/csrow3/edac_mode
   SECDED

SECDED. Just ask for SECDED.

> That's not SECDED, since it can't correct a bitflip that occurs somewhere other than on the link

You're just making up arbitrary rules. The term SECDED does not incorporate any guarantees about which part of a system it applies to. It's just a mathematical statement about the strength of the ECC in use plus the implication that detectable but uncorrectable errors are reported.

What you're looking for requires more words to fully specify, probably including the term "end to end".

Your mantra is sort of hilarious because with current technology SECDEC is the worst ECC you can buy. If that's what you are getting on a DDR5 server today, the most likely reason is your integrator has made a mistake.