The reason it got more cores is I believe the CPU die is the same as the 14900, but it just had some cores disabled. So they un-disabled them.

> The difference between 205W and 253W is only about 3.5% performance. The difference from 150W to 205W is about 10%.

I want the opposite of what Intel is offering for my home server. Give me lots of pcie lanes, but not insane power consumption.

https://www.techpowerup.com/310057/amd-zen-4c-not-an-e-core-...

https://images.anandtech.com/doci/17601/Core%20i9-13900K%20C...

https://images.anandtech.com/doci/17047/12900K%20Bounce.png

(I haven't seen results, but, I am guessing N100/N300 processors have better latency than this, and this is purely an artifact of alder lake still being kind of a shitty implementation from a bunch of teams that are flailing... it just looks good because the p-cores are good, but the rest of the product is shit.)

(if you have a N100/N300 and could spare a moment, you can answer this question with this tool!) https://github.com/nviennot/core-to-core-latency

Similarly, Apple's e-cores are really intended for background workers in phones, not interactive tasks, and not batch processing an intensive workload.

AMD's e-cores are literally just slightly lower-clocking/lower-cache/4-core-CCX versions of the normal cores, so, there shouldn't be this cliff. Being inside an e-core CCX should be the same as being on a non-big.little processor entirely, other than going back to a multi-CCX model and having a bit lower performance.

Similarly, in the long term, Intel is supposedly looking at something they call "royal cores"/"rentable units" where it's actually (eg) 3x little/1x big core in the same cluster, or some of the units can be paired together to work faster as a single execution stream. So you don't have the latency of flinging a work item all the way to some other stop on the ringbus, because the e-cores are right there and work in the same cache hierarchy/etc.

There is some iceberg-work there in terms of making the scheduling play nicely. But oh look, they've been working towards exactly that with the Intel Thread Director (tm) stuff. Everyone thought it was hideously overwrought for just some basic big.little design... and it is. But when you are scheduling 4 threads onto a core and 1 of them goes fast, the CPU itself will need to make the determination. This will actually vary over time too - sometimes you will have threads on the e-cores while you wait for memory access, etc, but then when they're ready they will burst on the p-cores and churn through their work, and go back to the e-cores.

(in a way you can argue this is the same vision that xeon phi was built for... xeon phi looks like a processor built for a world of intensive AVX-512 work segments, stitched together with highly-threadable low-performance IO segments/other work. Knight's Landing basically Silverton (e-cores) with SMT4 added (to an e-core, yes) and you get 72 of them, and the bulk of your work is happening in the AVX-512 parts stitched together by these scalar SMT4 threads. Well, Royal Cores are the same idea but with regular scalar code - put the hard parts in the p-cores and the easy parts in the e-cores, and run enough work to saturate it.)

But everyone is fishing at this same "p-cores churn through the hot thread and emit bulk work items, e-cores handle the bulk work out of a queue or something" model and that's just not tenable when the e-cores have this massive latency hit/etc. It's not that "e-cores are shit for games" it's that "having half of your processor have twice the latency and exist in a separate cache partition is shit for games"... same reason multi-CCD AMD chips don't do well in games.

https://pastebin.com/7m25RXTs

> core-to-core-latency -b 1 --csv >>core-to-core.log 2>>core-to-core_stderr.log

78.59179166666667,,,

77.05955166666666,119.60540999999999,,

76.81403166666665,76.47733500000002,76.56136166666667,

roughly 76-80ms latency core to core.

So maybe I just have overly rose-colored glasses about the e-core latency, maybe the latency is just ass.

Also, rustup, with visual studio forcing dx11 install or whatever, while doing windows updates, is just the best on a 120gb Liteon sata SSD pull with 4GB of memory on a J5005 lol. Can't even optane that shit to make it go faster because it doesn't have a m.2 lol

Power consumption or yield issues ???.

And probably this tends to understate things because that's Golden not Raptor cove. Intel went obscenely huge on caches with Raptor Cove too - they did the same thing as NVIDIA with Ada, and dumped an assload of L1/L2 cache on it too. I don't know off the top of my head but let's say 10-20% bigger for Raptor cores.

https://www.reddit.com/r/hardware/comments/qlcptr/m1_pro_10c...

In contrast Gracemont is much smaller - it is not quite "4x" as advertised, 4 is actually the number of cores in a Gracemont CCX/cluster, but the cluster is somewhat bigger than a Golden Cove core. So the actual core area is 3.26 Gracemont cores per Golden Cove core, and again, Raptor Cove is significantly bigger.

--

So the tradeoff is like - they could have done a 12P0E or something like that, for about the same area as a 8P12E. Which would still lose to a 16P0E Zen3 in multithreaded workloads, most likely.

That's the game Intel is playing - 8P is generally enough for games, but it's area-inefficient to keep scaling like that. But you have these other bulk tasks that just like tons of cores and don't care about peak performance, so, you have a mix of both. The E-cores give you more perf/area and the p-cores give you more peak perf for games/etc. So theoretically it's the best of both worlds, it's not as slow as a full e-core chip would be but it has a lot more MT performance than an all-P-core would.

Unspoken underlying problem being that Intel's P-cores are much, much, much bigger than the competition. Hence they have a much greater need to come up with a "compact" alternative than AMD does. Using that 1.8x logic scaling factor (which is optimistic), a Zen3-on-5nm design would be 1.72mm2 which is just about the same size as Gracemont. So Intel's "e-core" is about as big as AMD's p-core! Hence why they are much more focused on a whole new core design, where AMD just densifies the existing one (high efficiency/high-density libraries, reduced cache, reduced interconnect (back to zen2's all-connected 4c CCX instead of zen3's 8C ringbus-based CCX), etc). Squeeze that last 30% and call it a day.

On a more tactical level, I think it also is a move to force people to use Gracemont and start writing code for it. Long-term, your P-core being 3x the size of your competitors' is not sustainable and they need to pivot away from the existing P-core design (lakes/coves), it obviously is just a mess internally from 3 decades of tech-debt. Nobody really cares about the atom chips, despite them being pretty good for a long time now (my J5005 NUC made a great thin client during the pandemic, I use them for HTPCs, etc). Well, now you have to care, or you're leaving performance on the table on the mainstream intel chips. It's not just "intel loves big.little" or "needs big.little for area" but also "big.little" is a way for them to start getting the "little" cores into running real-world code.

(my suspicion is that this is a case of Conway's Law in action, and the architecture of the Lake/Cove family resemble the Intel organizational chart, and since Intel is a giant knot, that's the processor architecture they produce, and they've been doing that for at least 20 years. In hindsight Pentium 4 was the warning sign of the internal rot, they got it back together for a while but after the sandy bridge era they collapsed and everything since then is probably just more and more tech debt and kludges stacked on.)

--

Also, frankly, the e-core's "CCX" design makes sense. Tiering your interconnect/cache is what AMD has done very successfully - you have 2 CCXs per CCD (on zen2), 8 CCDs per socket. And that lets them decompose the interconnects into manageable pieces - 4 cores per CCX is a simple all-connected topology. Those talk to 4 quadrants on the IO die, which is a simple topology. If you want to talk to the other CCX, you have to go through the quadrant/IO die, so there is no "special case" there. It's all just a composition of simple pieces.

Ringbuses get annoying/inefficient past about 10-12 cores, which is why Intel abandoned them in server back with skylake. But a mesh of individual cores also has this huge latency penalty. What's the middle-ground? You group the cores into clusters/CCXs and you either have a mesh-of-CCX or a ring-of-CCX or some other tiered structure. And you can break the "tile" idea down into tiers too - a tile is a mesh of cores, and then you have a mesh of tiles, but these are separate logical tiers and don't need to interact.

It is the usual HPC networking problem - connecting 1,2, or 4 nodes is easy, with simple all-connected or hypercube topologies, with a small number of links. A hypercube requires only 2 links per node for 4 nodes. An all-connected topology requires only 3 links. And you can solve for modestly higher numbers with something like a ringbus (which gets a lot of flak but it's an extremely performant network structure, and AMD uses them too for their 8-core CCX). But that falls apart with higher numbers of nodes too and you need something that both scales in terms of network hardware/area/power, and also performs in terms of actual latency and throughput.

That's super difficult so the best strategy is to introduce this tiering. And AMD has meticulously stayed in the limit of "the IO die is a simple hypercube topology of quadrants" and "the CCX is a 4C all-connected or a 8C ringbus", and just composed these simple things together with tiering.

I think low-key Gracemont is important because it's Intel tinkering with the same concept - and they're doing mesh-of-tiles with sapphire rapids too (not sure what the topology is on each tile though). Because they can't have 14+ stops on the ringbus (memory controller, 12 cores, iGPU, etc) and the purist "mesh of single cores" topology obviously didn't work with skylake-SP.

--

Anyway, I wish they would do all-P-core too, and theoretically that exists, it's Sapphire Rapids, and there is a workstation/HEDT variant, it's just super expensive and has massive power transient problems (you need 500W of headroom, literally) that might be sending them back to the drawing board for another stepping. And there is also all-e-core chips too, that's Sierra Forest... but it seems like a tentpole customer pulled out (rumored to be facebook iirc) because Bergamo, AMD's compact-core based Epyc server chip, is more attractive. And so they have reduced the scope of Sierra Forest, it now tops out at 2 of the medium chiplets and the big chiplets are canceled entirely (where they planned to use up to 4 of the big ones).

MLID is such an unreliable source that I hesitate to recommend him, I like his content and listen to him a lot, but you really need to understand the broader context of the market/etc to know whether what he's saying makes sense. But he does tend to have some interesting guests who are usually way better than he is, and one of his recent guests was a boutique PC builder who specializes in digital audio workstations (which need to be super low latency/etc). And they talk about Sapphire Rapids workstation and some of the things being discussed around it.

https://www.youtube.com/watch?v=_HJu5xt43iQ&t=3603s. (and the previous segment too)

Sierra forest discussion: https://www.youtube.com/watch?v=QlTZCDEFUFg&t=4200s

General intel discussion: https://www.youtube.com/watch?v=BNXlRdAKWTE

(PS don't forget agner fog's microarchitecture, you might be one of today's lucky 10,000! https://www.agner.org/optimize/microarchitecture.pdf )

Consider also scihub:9780849337581 for a general overview of architecture approaches in general.

It is funny that we keep reapproaching this "barrel processor" design that the CDC 6600 started so long ago. That "Vector processor + peripheral processor" design is super interesting. Nerds are attracted to this design like moths to a fly - it has been repeated and echoed in Sun Niagara, AMD Bulldozer, Xeon Phi, and now Royal Cores/rentable units/zen4c/5c/etc.

https://cs.uwaterloo.ca/~mashti/cs850-f18/papers/cdc6600.pdf

https://archive.computerhistory.org/resources/text/CDC/cdc.6...

http://www.bitsavers.org/pdf/cdc/cyber/cyber_70/60045000_660...

Very interesting source material etc, see how they talked about their own processors.

Alder Lake 8P8E: 215.25mm2

Alder Lake 6P0E: 162.75mm2

Raptor Lake 8P16E: 257mm2

For comparison:

8700K: 149.6mm2

9900K: 174mm2

10900K: 206.1mm2

Zen2 CCD: 74mm2

Zen3 CCD: 83.74mm2

That's actually pretty big for a consumer processor already. And it's all in monolithic 5nm(-tier node), which isn't cheap even if it yields fine. So them having a uarch that's at a pretty bad area disadvantage isn't good, and tbh they obviously aren't delivering on any kind of efficiency promise.

Physics is getting hard and wafer costs are spiraling pretty bad, which is why AMD is exploring advanced packaging/etc. Doesn't always work though - like RDNA3. Data movement still seems to be very expensive, although 2.5d and 3d stacking (and direct-bonding) will mitigate this somewhat. But advanced packaging means moving a lot more data, and you have to be careful of what lives on what side of what links. Cache being on the other side of the infinity links (not infinity fabric!) in RDNA3 seems like potentially a specific problem with the design, since you pay the cost for the data movement to the cache and not just the data movement for the memory.

I think you're right they probably could do it if they wanted etc, maybe sell it as a pseudo-HEDT (especially if you can glue together a pair of dies directly to 2x the normal core count - and if you can glue together 2x16C all-P-core designs that's fine for HEDT for a lot of things imo!). But the price would probably be fairly high (16C would be like, probably $700-900) and the power would still be quite high (intel does not win at any power bracket right now even with limits, it's just less bad if you limit it to 150W), etc. Maybe some of the power stuff would go away if you got rid of the split-brain big/little clusters on a ring thing, but, even if you went with 16 P-cores on a ring, the latency would still go up a lot, and you'd notice it because the stuff you want it for is gaming/etc. The latency would hurt gaming IPC a decent chunk imo, or you'd have to go to a double-ring like broadwell.

It's a mess and this is the point where the ringbus scaling craps out, is my point with the latency discussion. It seems hard to have more than about 8C or 12C per "tier". Even Bergamo (AMD's new e-core variant of Epyc) is 16C of Zen4C per CCD, but it's 2 CCXs of 8. Broadwell dual-ringbus is 2 tiers of 12 cores each. Etc. The subsequent Intel chips moved to the mesh. You can add more tiers of 8-12, but about 8-12 nodes per tier seems to be the limit that scales well due to interconnect bandwidth/etc, just historically imo. Interesting convergence.

https://www.anandtech.com/show/10158/the-intel-xeon-e5-v4-re...

I think strategically they want and need to keep selling the e-cores though, it's not what's right for you, it's what's right for them and their migration path. Some of these pieces it's hard to see how you do everything in a single go - it's tough to go from "everything is the same" to "lol CMT with 3 slow/1 fast thread controlled by this thread director that wants to talk to your OS scheduler". But the theoretical end-state of "big.little within a core cluster" or "within a CMT core" is pretty neat at least, that would mitigate the latency problems of dedicated "little core clusters".

Now again, to say something nice here: the p-cores are pure out-of-order monsters. Very wide decode units, lots of execution resources, etc. It is the same as the "zen4 vs zen4-X3D" split, stuff that prefers zen4 over x3d also really prefers raptor cove, it's an execution monster and it does it all on just 8 p-cores. it just also uses more energy to do it, and cache can handle some other situations where the working set helps cover some useful working set. And the e-cores do give you a ton of the performance equivalence of having a wider AMD processor in MT workloads (if they're not latency-sensitive, ie cinebench and video encoding), just not at particularly great power compared to 16 p-cores clocked much lower.

I like my Atom processors a lot (and I've looked seriously at denverton etc). They're not bad cores at all, but Alder/Raptor just put them in the worst possible place. I would have loved the idea of Sierra Forest-HEDT with like 192 / 256 cores (or whatever specifics) enabled or whatever, if they could get that to a relevant price for enthusiasts it'd be amazing, the HEDT market is super dead and the e-cores are good enough nowadays. That would be a super high-value place to put a product, if it's not moving adequately in the server market etc. Give me 5820K level value for something the client platform cannot do, and Intel benefits from actually getting a foothold on a market that is willing to tinker and build stuff.

But everything intel does has come so late that it almost doesn't matter, it's a sidegrade at best, at much worse efficiency etc. Just buy a 7700X or 7800X3D or 7950X/X3D. Let alone the slaughter in the server market etc. Sapphire Rapids is not great either, lots o weird power shit, and maybe it needs another stepping to fix it? ok, or, if you're a hyperscaler, amd will ship you zen5 samples probably within the next 3 months, and they can actually execute and deliver.

Hard to see that changing anytime soon either, I don't even see green shoots, I think they're in a death spiral tbh. I see the 2.5gbe nic team failing over and over (I225/I226), I see sapphire rapids taking far too many steppings and base die changes, I see DLVR still not working, I see no plan for AVX-512, I am guessing they have continual problems with integration/packaging, I see every product being a one-off with no reusability, etc. They're too important to let go under but they're in deep shit and they have to do a turnaround on an understaffed underpaid employee force etc, while battling deep internal-culture rot and middle-management warfare etc. It's gonna be a while before they're relevant imo.

They have some neat ideas but AMD is gonna leap forward again with Zen5 too, everyone has neat ideas that will be coming to fruition in 3-5 years. Zen4 was the easy stuff (a straightforward port of zen3 to 5nm, with DDR5, with AVX-512, and some minor tweaks to open up architectural or timing bottlenecks to push clocks etc). All the interesting stuff is coming next year in zen5, imagine this 14th-gen stuff going up against zen5 being probably 20-30% faster in general performance. They're in trouble, everywhere, every product segment.

https://en.wikichip.org/wiki/intel/microarchitectures/alder_...

https://en.wikichip.org/wiki/intel/microarchitectures/raptor...

https://www.techpowerup.com/297506/intel-raptor-lake-core-i9...

https://en.wikichip.org/wiki/intel/microarchitectures/coffee...

https://www.techpowerup.com/267649/intel-core-i9-10900k-der8...

https://en.wikichip.org/wiki/amd/microarchitectures/zen_2#Di...

https://wccftech.com/amd-ryzen-5000-zen-3-vermeer-undressed-...

https://wccftech.com/amd-epyc-bergamo-cpu-die-detailed-16-ze...

(just wanted to call out: wikichip is a lovely site, lots of randomly useful information there. and wikipedia also has a number of useful lists of cpus/gpus/mobile SOCs/etc with characteristics listed, and good sources for CUDA compute capability etc. Don't sleep on wikipedia as a quick reference for what the boost is on random xeon sku xyz, and so on.)

https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_processo...

https://en.wikipedia.org/wiki/Intel_Graphics_Technology

https://en.wikipedia.org/wiki/Tegra#Models

https://en.wikipedia.org/wiki/CUDA#Version_features_and_spec...

That's a pretty big gain for better yield/tighter undervolting over time, that's a large chunk of the processor's power consumption (which HUB does not bench separately). I'm waiting to see the meta-reviews come out but that's tentatively interesting.

I totally bet they did get DLVR working and just immediately spent it all on higher clocks and a few more cores in key segments to stay ahead of AMD in the "top" segments (or, the benefits of the stepdown are minimal when you're clocking very high). It looks like another 12900K/13900K where the top SKU is just clocked beyond all insanity but if you set a normal power limit it's fine. Actually substantially better than 12th/13th gen in efficiency, at iso clock/cores.

https://www.techspot.com/review/2749-intel-core-14th-gen-cpu...

DLVR is the continuation of the FIVR technology from Skylake-SP. I know I've read some good discussion on the topic recently but I don't remember the specific trajectory of the tech. But Alder Lake was supposed to reintroduce it (confirmed in BIOS options left in early Asus bios) and Raptor Lake was supposed to introduce it again... third time's the charm, seemingly.

https://www.tomshardware.com/news/intel-dlvr-fused-off-in-ra...

https://twitter.com/Underfox3/status/1428233148870111233

https://www.freepatentsonline.com/20210208656.pdf

It just also does not really matter because AMD is making progress too. These 14th-gen will have to go up against Zen5 next year, even if Meteor Lake does get into socketed chips at some point (which will be a new socket, lol) it's gonna be in a much different competitive atmosphere.

Strix and Strix Halo should be sick and should be very legit Apple Silicon competitors, for extreme enthusiast workstation laptops etc with socketed dual/quad configurations to 512GB/1TB respectively, or more, and big caches, with AI accelerators etc.

Intel needs to get products consistently working and consistently out on time. It's not that their products are awful, per se, but Meteor Lake is going to be perceived way differently coming after Zen5 launches etc. Server Zen5 will not be that many quarters away. Etc. The 2.5gbe still has problems after like 6 public steppings. Etc. There clearly are still problems in execution.

Clearly, the correct move is to buy 13th gen parts at their current street prices; or maybe Ryzen depending on what your priorities are. The only good news is that it's hard to go too wrong in this era; I've had great success with CPU upgrades and new boxen in the past few years on both sides of the aisle.

I find it amusing that my absolute best intel desktop chip you could buy in 2019 would now be considered a low power chip with it's 95W TDP.

I don't know how good of a value the 7700X bundle is, but my problem is I always want more cores because I am usually compiling code. I loved the 5950X, a very fast and power efficient CPU, so my likely upgrade path is probably the 7950X or TR or whatever CPU takes the "productivity" crown next. And hopefully, by the time I'm in the market again, MicroCenter will have another unreasonably good deal available.

Also, 7700x buyers can expect CPU upgrades for a generation or two on the same motherboard. Intel's 14000 series (13000 part 2) is the end of the line CPU upgrade for the 12000 buyers.

My plan is to get the 7700X bundle, which for $400 with board and 32GB DDR5 is a steal, then when AM5 is replaced get a new CPU from the final generation.

Was the 9700K -> 7700X upgrade a nice jump? I've been running MSI afterburner and keeping an eye on GPU usage and am often only using ~80% while well under my monitor's FPS limit. It doesn't show any CPU cores pegged but I assume that's my bottleneck.

I think if I buy new I’ll go ddr5, otherwise I’ll stick with whatever is around. But people in the bay are trying to pay rent with their PCs and want way too much for the age of components they have. Back on the east coast the same pcs go for 200 less at least. Makes negotiation a bit difficult.

This is normal in Australia, but that's due to the size of the country and the sparse population in some areas. Our prices are a rip-off equally everywhere: https://en.wikipedia.org/wiki/Australia_Tax

-vicuna

I'm not sure what footnotes the earlier poster meant. One might be that the AMD model numbering is a bit obscure. You need to look closely that you are getting a Zen 4 core in your Ryzen, with the same model line mixing different CPU and GPU architectures in different models. I don't know if there are programmer-visible differences in what AVX-512 means to AMD vs Intel...

oh... i missed the fact that they said ryzen. oops. sorry

-vicuna

this is currently their best selling point, this better not ever change

-vicuna

https://www.youtube.com/@GamersNexus & https://gamersnexus.net

The intro in the recent video about the 14700 was quite amusing:

https://www.youtube.com/watch?v=8KKE-7BzB_M

For example, AMD mobile 5XXX series contained a mix of Zen 2 and Zen 3 parts. For example, the 5500U is a Zen 2 part (but the 5500H is Zen 3). The 5700U is Zen 2 (but the 5600U and 5800U is Zen 3).

This isn't to defend Intel - this launch is pretty bleh.

For the current mobile 7000 series there is a mix of zen4 and zen3+ that confuses consumers and I think is worse than just releasing the same CPUs with a different number. For example

https://www.notebookcheck.net/AMD-Ryzen-7-7736U-Processor-Be...

I want to buy a used 15" Dell XPS. What processor should I buy? I think they range from i7 to i11 or something.

I do nothing fancy, don't play computer games or something, no video editing.

Also there are factors like battery consumption. The lower-end CPU uses less power so the battery lasts long.

Same can be said for GPUs but if you play games you probably want NVIDIA GPU even though it is worse battery-wise.

Anything older than 8th Gen Intel processor won't run Windows 11 without some hacking. Sure, Windows 11 isn't all that well liked, but it's not a good idea to buy a system that won't even run the newest OS. You're going to be out of support before you know it. 8th gen processors were released in 2018.

Also, a ten year old system is likely to have a spinning hard disk instead of an SSD. Spinning hard disks are frustratingly slow.

Also, before the 8th gen release, you couldn't even easily find a 14 inch or smaller laptop with a 4-core CPU because of the cooling requirements. I think a 4 core processor is becoming somewhat of a necessity these days.

But anything at all that runs Windows 11 will almost certainly do you fine. Just make sure it has at least 8GB of RAM. That is the minimum I would use Windows 11 with. And an SSD.

I'm working on an old 2012 Lenovo here that I put 16GB RAM and an SSD in and I'm editing 4K video. It's not quick, but it will do it. Certainly works with me having literally 200 tabs open in Chrome, Visual Studio, Photoshop etc.

And just the windows explorer is slow. Hurts my pace. Can’t figure out what is happening.

I have a 6 year old 7th gen i5 laptop here with 16GB + SSD in it and it is smooth as butter with stock Windows 10 and about a billion things going on. I have it running two screens and I use it for editing 4K video, doing livestreaming etc. In fact, I have a second identical one with only 8GB in it and it is perfectly fine as long as it doesn't go to swap.

The SSD I put in is a $10 job from Amazon.

I wonder how to get some sort of system-wide profiler that will show where the hang-up is?

The 6th gen laptop darling was the i5-6200U which has 4 thread (dual core) CPU. I have an Asus Zenbook with one of those and unless I want to compile a kernel in a hurry it's still perfectly functional for all tasks. You can get the same CPU in a second hand ThinkPad X1 Carbon for well under US$200 these days.

I'd probably draw the line at Sandy Bridge (2nd gen) as they're the first with AVC and VC1 video decode. Haswell (4th gen) adds come VP8/VP9 decode on Linux. H265 doesn't arrive until 7th or 8th gen (but if you're building a TV box for that, get a Pi 4 which does it perfectly at 4K).

This i7-14700K has bumped frequencies, added E cores and increased "Smart Cache" (3MB) and total L2 cache (4MB) and uses the existing socket. It's a fine refresh product that will do what it says on the tin for years, and given that it is a refresh of an existing, mature product, it will do so with the least possible friction.

"Pointless" in the context of the hardware that already existed at the time of it's release. Not "pointless" as in it doesn't function as a processor.

I heard that Intel might have gotten their Digital Linear Voltage Regulator working which would decrease power consumption. It was disabled in 13th gen because it was broken.