Re:Analyzing the complexity of various RISC/CISC architectures
by zozbot234 on Saturday December 31, 2022 @05:59PM
(#34201630)
Yes but RISC-V is very risc-y by the criteria Mashey proposes here. The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes. That's still very low compared to historical CISC. And I think the atomic instructions do RMW to memory, but they carefully avoid complicated address modes; they even dispense with register+immediate offset.
Re:Analyzing the complexity of various RISC/CISC architectures
by Tuna-Fish on Saturday December 31, 2022 @09:09PM
(#34202861)
> The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes.
They will have a third very soon. The encoding space for 4-byte instructions is almost spent.
Re:Analyzing the complexity of various RISC/CISC architectures
by kjs3 on Saturday December 31, 2022 @06:22PM
(#34201774)
Comp.arch from the '80s thru the '00s is full of gems from actual CPU architects and other folks who deeply understood what they were talking about. Even (maybe especially) when you had two pros who had very different philosophies, they brought so much fact and experience to their posts you could really see how and why the other side saw things. Now it seems like virtually all processor comparison is some variation on "who runs $HOTGAMESOFTHEMOMENT one FPS faster...that must be the best one".
Re:Analyzing the complexity of various RISC/CISC architectures
by mhh__ on Saturday December 31, 2022 @07:26PM
(#34202232)
Games are a reasonably good stress of a CPU in real life. Most modern bench's are really unrealistic unless you're buying CPUs for raw compute (e.g. 100% util 24/7)
Re:Analyzing the complexity of various RISC/CISC architectures
by kjs3 on Sunday January 01, 2023 @12:05AM
(#34203770)
Games are a reasonably good stress of a CPU in real life.
No they aren't. In 'real life', games, especially high resource games, are inconsequential compared to, say, performance of Excel, Word or web browsing for the overwhelmingly majority of users.
Re:Analyzing the complexity of various RISC/CISC architectures
by xanathar on Sunday January 01, 2023 @05:42AM
(#34205290)
That criteria would just say "every CPU is ok" because ultimately only potatoes are unfit to run those problems. And nobody wants a review website posting "just buy a Celeron or whatever costs less and be happy" for 15 years straight.
On the other hand, measuring on, say, protein folding isn't likely to gather a lot of interest because most people are not buying laptops to run HPC research.
So, ultimately the reason videogames (and video encoding, compression, image processing and a few other workloads) are chosen is because they are workloads where the CPU really makes a difference and is interesting to the average reader if not because it's their problem, at least because they are close enough to be understandable.
(A separate 10 page post would be required to dig into the GPU role and impact of those tests)
Re:Analyzing the complexity of various RISC/CISC architectures
by dboreham on Saturday December 31, 2022 @09:05PM
(#34202841)
Reading Mash's posts on comp.arch led me to drop my resume off at reception at the office on Arques Ave in the hope of finding a job there. Probably 1989. Didn't get a call back. Good times though.
Re:Analyzing the complexity of various RISC/CISC architectures
by ajross on Saturday December 31, 2022 @11:43PM
(#34203685)
And one that largely obviates almost every point made. In point of fact, in the 31 years (!) since this was posted the "clearly most successful/performant/useful/best" processor at any moment has almost always been an implementation of one particular CISC ISA that violates almost every rule Mashey posits.
This happened to look right in 1991 because SPARC and MIPS were riding high at that moment in history. Both would fall behind x86 a few years later.
And more to the point: this only looks right at this particular moment because Intel fell off the edge and Apple jumped ahead with a TSMC-manufactured part. But that's almost entirely down to process technology. If Intel was using TSMC's process then it's likely that the M1 switchover never would have happened.
Re:Analyzing the complexity of various RISC/CISC architectures
by ajross on Monday January 02, 2023 @10:58AM
(#34219291)
One example over three decades doesn't prove much. As pointed out, in 1992 the best CPU in the world was a SuperSPARC, with the MIPS R4000 about to leapfrog it. It didn't stick. I didn't say x86 offerings were uniformly and always better than RISC ISAs. I said it was almost always better, which sort of demolishes Mashey's arguments about the inherent superiority of the ISA design.
And in any case you're wrong on the facts. The M2 and Zen 3 cores are not being fabbed on the same process; AMD is still on 7nm for its CPU products vs. 5nm for Apple. Their use of 5nm is exclusively for GPUs so far.
Re:Analyzing the complexity of various RISC/CISC architectures
by Gibbon1 on Sunday January 01, 2023 @05:41AM
(#34205285)
I think the issue is due to the way modern memory architectures work alignment restrictions don't buy you much. In particular because memory accesses suck in a whole cache line. As long as all the data is in the cache line it's easy enough to swap bytes around on the fly.
Makes sense as a hardware designer to be able to pick a power- and space-efficient chip.
Mashey also had thoughts about that: https://yarchive.net/comp/mips16.html
Likewise for atomic operations: https://yarchive.net/comp/ll_sc.html
They will have a third very soon. The encoding space for 4-byte instructions is almost spent.
John Mashey on RISC/CISC - https://news.ycombinator.com/item?id=9811397 - July 2015 (4 comments)
Others?
No they aren't. In 'real life', games, especially high resource games, are inconsequential compared to, say, performance of Excel, Word or web browsing for the overwhelmingly majority of users.
On the other hand, measuring on, say, protein folding isn't likely to gather a lot of interest because most people are not buying laptops to run HPC research.
So, ultimately the reason videogames (and video encoding, compression, image processing and a few other workloads) are chosen is because they are workloads where the CPU really makes a difference and is interesting to the average reader if not because it's their problem, at least because they are close enough to be understandable.
(A separate 10 page post would be required to dig into the GPU role and impact of those tests)
This happened to look right in 1991 because SPARC and MIPS were riding high at that moment in history. Both would fall behind x86 a few years later.
And more to the point: this only looks right at this particular moment because Intel fell off the edge and Apple jumped ahead with a TSMC-manufactured part. But that's almost entirely down to process technology. If Intel was using TSMC's process then it's likely that the M1 switchover never would have happened.
And in any case you're wrong on the facts. The M2 and Zen 3 cores are not being fabbed on the same process; AMD is still on 7nm for its CPU products vs. 5nm for Apple. Their use of 5nm is exclusively for GPUs so far.
More goodies: https://yarchive.net/comp/index.html
One thing isn’t - 5a, unaligned access. Some modern RISCs allow this, probably because there’s enough code out there that does it.