Yes but RISC-V is very risc-y by the criteria Mashey proposes here. The one thing that arguably doesn't completely fit is the multiple insn sizes, and even then real-world RISC-V implementations have only two, at 2 or 4 bytes. That's still very low compared to historical CISC. And I think the atomic instructions do RMW to memory, but they carefully avoid complicated address modes; they even dispense with register+immediate offset.