I'm not totally convinced that'll happen in the desktop space. Embedded, I completely buy it, but I have read fairly convincing arguments that ARM might be a better ISA for really high-performance architectures. RISC-V also seems to value compressed instructions far too much, so we could see a high-performance fork of RISC-V?
Given how much cruft x86 has, there's a comments about world class experts above saying the gap between ARM and x86 is maybe 5%, at best, and probably less.
There's realistically probably no reason RISC-V cannot work, expect that the number of techniques needed to implement a leading edge high performance evaluator is enormous.
RISC-V has a few ISA advantages over ARM64 (mainly the variable length instructions, which provide instruction density that's comparable with x86 while still being very easy to decode) but meaningful competition would have to come from something more like the upcoming Mill architecture - VLIW-like power efficiency with the same flexibility and IPC as current OOO designs.
RISC-V has some bad ISA disadvantages like needing three (!) instructions for array indexing: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99...
Isn't Mill eternal vaporware?
I'd be willing to bet Apple will catalyze that change as well.
Re:Rendering on the Apple M1 Max Chip
by fartcannon on Monday October 25, 2021 @10:25PM
(#28995727)
Only if they can lock it down.
Re:Rendering on the Apple M1 Max Chip
by GoOnThenDoTell on Monday October 25, 2021 @11:39PM
(#28996151)
They can make their own extensions
So now the wheel turns and someone will have to predict how long it takes before RISC-V overtakes ARM.