That's the virtual address space. A page table entry has enough bits to have a 64-bit physical address space, it just wouldn't be able to have it all mapped at once in the same virtual address space. Although CPUs don't have 64 physical address lines yet, there's nothing fundamental in the x86 architecture preventing them from doing so.
Intel have already implemented 5-level paging, which would give a 2^57 bit virtual address.
Also, this wouldn't be the first time that the x86 has supported more physical memory than virtual. PAE allowed for 64GB of RAM on a system with a 32-bit virtual address space.
While we're here I hope anyone can explain to me why Cooper Lake Xeon parts are listed as supporting 4.5TB of DDR4.
Answering self: the 4.5TB support is mostly Optane memory, not DDR4.
So the number of bits in an n-level system is 9n + 12.
9x5 + 12 = 57
On 32-bit systems the number of PT entries was 2^10, which is why they could have a 2-level system. 10x2 + 12 = 32.
IBM Power System E980, max ram: 64TB.
Expanding from 48 toward 64 bits isn't difficult.
$ echo '(32 * 2^40) / (8 * 2^30) * 3' | bc
12288Here is the datasheet for a 128GB dimm from 2017 [1], which shows 3.4A IDD0 (normal operation) on the 1.2V rail at the highest speed of DDR4-2666, and 0.2A on the 2.5V precharge rail for a total of just over 6W. Also worth noting is that is a LRDIMM, which draws more power from the DC rails due to the additional buffering. A normal RDIMM draws a bit less static power.
Compare to a manual for a similar vintage 32GB stick [2], which consumes 2A on the 1.2V rail and 0.1A on the precharge rail for a total of a bit under 3w. One quarter the capacity, but still half of the power draw.
[1] https://www.samsung.com/semiconductor/global.semi/file/resou... [2]https://static6.arrow.com/aropdfconversion/d3b3ce1d78b0ad7d3...
Thanks for doing the math on the power story. I didn't realize about the scaling.
Also worth considering that 32TB of DRAM would draw over 12kW, just sitting there.