Re:DDR5 Memory Specification Released
by kryptiskt on Thursday July 16, 2020 @03:21PM
(#23862774)
Ice Lake added 5-level paging and 56-bit pointers, so they can address 128 PB: https://en.wikipedia.org/wiki/Intel_5-level_paging
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Hey, I'm a bit late, but it's 57-bits. On 64-bit systems page tables have 512 = 2^9 entries and page frames are 4096 = 2^12 bytes long.
So the number of bits in an n-level system is 9n + 12.
9x5 + 12 = 57
On 32-bit systems the number of PT entries was 2^10, which is why they could have a 2-level system. 10x2 + 12 = 32.