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Re:DDR5 Memory Specification Released by messe on Thursday July 16, 2020 @03:22PM (#23862790)
> You would need a new CPU that doesn't yet exist to address 32TB of memory per socket. Existing parts can address 1TB (Intel) or 4TB (AMD). x86-64 has an ultimate system limit of 256TB, due to its 48-bit virtual address space.

That's the virtual address space. A page table entry has enough bits to have a 64-bit physical address space, it just wouldn't be able to have it all mapped at once in the same virtual address space. Although CPUs don't have 64 physical address lines yet, there's nothing fundamental in the x86 architecture preventing them from doing so.

Intel have already implemented 5-level paging, which would give a 2^57 bit virtual address.

Also, this wouldn't be the first time that the x86 has supported more physical memory than virtual. PAE allowed for 64GB of RAM on a system with a 32-bit virtual address space.

Re:DDR5 Memory Specification Released by jeffbee on Thursday July 16, 2020 @03:33PM (#23862922)
It costs them money to add physical address pins, though.

While we're here I hope anyone can explain to me why Cooper Lake Xeon parts are listed as supporting 4.5TB of DDR4.

Answering self: the 4.5TB support is mostly Optane memory, not DDR4.

Re:DDR5 Memory Specification Released by chacham15 on Thursday July 16, 2020 @08:23PM (#23865527)
The Google Cloud machine type m2-ultramem-4164 has 11,776 GB of memory. How does it accomplish that then?
Re:DDR5 Memory Specification Released by jeffbee on Thursday July 16, 2020 @08:34PM (#23865617)
4 sockets?