There isn't any feature of the transistors taht are 7nm wide, the smallest feature IIRC is the interconnect, which is about 30n-40nm. "7nm" is marketing wankery. https://en.wikichip.org/wiki/7_nm_lithography_process

Not quite accurate. There are a number of dimensions involved. Interconnect is definitely not the smallest.

This article show some examples: https://www.semiwiki.com/forum/content/3046-new-frontiers-sc...

If you look at the SRAM bit cells, they halved in area from 28nm to 14nm, and halved again from 14nm to 7nm. This is likely due to metal interconnects or other features only halving in spacing going from 28nm process to 7nm. So the scaling almost appears to apply to only one dimension (full linear scaling of two dimensions would have quartered the cell area at each step resulting in a 16-fold total reduction). But it is still scaling nevertheless.

Wait for 3d sram

There are different features sizes in the Z direction and different feature sizes in the XY plane. When it comes to XY, the smallest features size is probably the gate length. When it comes to Z, the gate oxide width is probably the smallest at 1-2nm. We have something called atomic layer deposition which gives control over single atomic layer thicknesses.

Well that's annoying. How is anyone supposed to judge anything if they just make numbers up?

Smallest feature size no longer correlates with transistor density in recent years. So manufacturers just use the number to convey increases in transistor density.

See https://en.wikichip.org/wiki/technology_node#History

That's why they do it. The sizes of Intel's 10nm is similar to or slightly smaller than everyone else's 7nm. Compare https://en.wikichip.org/wiki/7_nm_lithography_process and https://en.wikichip.org/wiki/10_nm_lithography_process .

I think bits of SRAM per unit of area is a benchmark that some people use, as it corresponds to something that's meaningful and measurable.

The problem is even that is flawed as things are going three dimensional.

So just start measuring in bits of SRAM per unit of volume?

That's a problematic metric as well because we don't know how much area the assist circuit takes up. Modern high-density SRAM cells cannot operate as is, they need an assist circuit to compensate for variations. For example for Intel's 10nm SRAM, they claim 77% area effiency (https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-inte...). But without those values, just bits/mm2 or so is problematic.

Hopefully their customers are more sophisticated than designing their chip based on a single number.

Well, after a while or is sort of public knowledge that 10nm Intel is about the same as 12nm AMD, etc.

But yes, the industry needs standardized advertising practices badly.

Uh, it's the other way around. 10nm Intel is 7nm global foundries. 22nm Intel is superior to 14nm global foundries.

Intel is the one that doesn't fudge their numbers.

Intel still fudges their numbers. They just fudge their numbers less than everyone else.

How so?

The numbers don't seem to have much relation at all with all of the real process node numbers.

Even Intel's numbers are just marketing, however.

Everyone is fudging the numbers...

SemiWiki has a good overview of Intel 10nm vs GF 7nm:

https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-...

For a while I think it was the other way around: Intel's processes were, in practice, actually substantially less dense than their competitors at the same nominal process node size.

>standardized advertising practices

Oh man, I wish this would happen in any industry...sadly, advertising doesn't seem to see any benefit. Why standardize when you can differentiate?

Thanks, kinda ruined my day but I learned something.

I've always assumed that "XX nm" doesn't represent the geometry of any particular feature of the end product, but something related to the wavelength of the radiation used for the imaging process.

Maybe it corresponds to the principle emission line of the light source (synchrotron?) In spectral terms, 7 nm is near the border between hard UV radiation and soft X-rays.

This is not correct at all.

Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI - it's both fascinating and terrifying the trouble that EUV brings) and mirrors since pretty much all matter is opaque to EUV light.

It's a bit maddening to think that features that much smaller than the wavelength of light used can be patterned with that light source, but we've made a science out of it over the past decade with multipatterning and immersion lithography.

"but we've made a science out of it"

Not just science, but working, high volume, commercially viable production processes. The science itself is extremely impressive, but then adding commercial requirements and pull it off. Over and over again.

Imaging presenting the idea for that light source. "How about letting droplets of molten tin fall through a vacuum and then blast it with CO2 lasers."

BTW: The light must be blinking, right? In time with the frequency of the droplets.

>- it's both fascinating and terrifying the trouble that EUV brings

It is only peanuts in comparison to what is to come. The "nuclear option" on the table is to build a whole fab around a freaking synchrotron light source.

I watched the video recommended by awalton, and it's definitely as insane as he says it is. I can't believe a synchrotron would be that much more expensive, considering that a single storage ring can have an arbitrary number of output ports.

The main issue with using a synchrotron or Free Electron Laser EUV source might not be so much about the technology, but more about the mindset of the clients (Samsung, TSMC, Global Foundries, Intel). Up until now lithography has been something they would buy as a "box" which would be shipped to their fab, "plugged in" and commissioned.

A Free Electron Laser EUV source would be a facility on it's own, similar in size to a small powerplant built adjacent to your fab, and multiplexed to a dozen or so EUV wafer scanners, that's quite a different endeavor.

And after that, and few EUV multiple patterning litho generation, lies a pitch black abyss called Deep X-Ray Lithography, the only thing that can push things closer to 1nm

Great movie. Those machines are monsters. A 2m high machine that sits inside the ASML machine. And is fed laser light from something like a shipping container in the basement.

So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength?

I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.

It's worse than that... there's not jist an industry group (ITRS), there's also the foundries making it up themselves. They're buying similar equipment and selling similar transistor densities (except for Intel which has finer geometries and higher densities for a given node), but few are directly compatible on density, clock-rate, or power consumption after 28nm.

https://en.m.wikipedia.org/wiki/International_Technology_Roa...

Scalling really started falling apart in the late 90s around .25u, and then (incidentally) about the time CPU MHZ stopped scaling... by 65nm both gate and transistor length got wonky. Then after 28nm they moved to fin-FETs and multi-patterning making comparisons even more difficult.

https://semiengineering.com/a-node-by-any-other-name/

It used to be a specific feature size: the length of the gate. But, even as the wheels came off of that pretty quickly, the convention stayed pretty simple and familiar: each process node halves the size of the one before it - you can print double the number of transistors at the smaller process node. To make the math work out, that means each process node "name" is sqrt(1/2) ~= 0.7x smaller than the last, which gives you the easy-to-follow node names from 3um to about 3nm (when people tend to switch to ångströms or picometers since it moves the decimal kindly).

Even as things got sticky due to advancements in transistor construction meaning that old metrics like gate length were obsolete, we were still roughly following the trend laid out ahead of us for decades. A new process would double your density, letting you roughly cut the size of your old chip in half.

...Until a few fab companies just up and decided "You know what, fuck it, we can't actually catch up to Intel, but if what if we just... say that we did?" (...and I wish I was kidding. Take a look: https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jp... vs https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jp...).

So pretty quickly, TSMC decided that they'd just advance the node table, despite not actually increasing the density by double as you'd expect. "Next generation" 20nm processes became "16nm" and "14nm" on marketing docs, despite the process capabilities not changing that much (or even at all in some cases), with the only thing close to a justification given is that "FinFETs are different. They perform better than planar FETs so we should be able to give them a new node name." GloFo and Samsung quickly took the bit and followed their lead as they began FinFET manufacturing.

And apparently since nobody blinked an eye or set off alarm bells about these fabs basically lying about their capabilities, they got away with it and are now continuing the trend downwards. "10nm" processes from TSMC, Samsung and GloFo measure up to Intel's 14nm, and now "7nm" processes measure up to Intel's 10nm. It's actually pretty surprising Intel hasn't thrown up its hands and joined them on the fun, or even come up with their own marketing spin on it yet. "Intel's new 7nm-xtreme manufacturing process (actually it's just 10nm+)" or whatever.

Who exactly would be responding to these alarm bells?

If I'm making a chip I want to use the node that best fits my product. Might not even be the latest one. But if they offer me 2x the memory destiny, 1.6x the logic density all at the same/lower power - I'll take it! Sure, the tracks are huge and I need a huge tall stack-up but that's not really my problem. I really don't care what marketing speak they use to refer to it. I have zero interest how long the gate is, I care about what chip I can make with this.

And Intel can do what they want. Their fab offering is very uncompetitive.

Intel's nm numbers are also pure marketing, I believe.

He says they hope to do 100 wafers per hour. I wonder how many dies will be on a wafer.

With current technology, a wafer is 10" in diameter (254mm), the aperture size limiting the die size is around 900 mm^2, so a chip is at most about 30x30mm. This would make it about 60-70 chips per wafer at maximum chip size (e.g. high end GPU). Most chips are a lot smaller, but there's a ballpark figure for you.

Chips are square but wafers are round, so there's a lot more wasted area with large chips.

In a sense it has been the "free lunch" of the industry, much like stored energy in hydrocarbons has been for manufacturing in general.

But the supposed exponential curve that stock markets loves to salivate about seems to once again turn into an S curve.

> Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades.

I would argue that for software it had the opposite effect, and has led to layers upon layers of crap. No need to ever fix that when you can rely on the next cpu being twice as fast.

Don't forget that optimization also costs time. Performance improvements just shifted the equilibrium between optimization and output. In the world where every programmer was forced to optimize their code, we'd have a lot less code.

From your lips to God's ears.

This talk host said he doesn't believe 5nm will crack (unless major electronics breakthrough)

https://www.youtube.com/watch?v=JpgV6rCn5-g&t=1136s