Just want to let you know, as a person that worked at intel at one point -- 10nm is already plenty hard. @ 10nm and below, engineers/designers at intel (and a bunch of smaller more agile companies intel works with) are at this point just fighting physics as we know it at this point.

There are promising technologies coming about, but since they're so different the amount of time it takes to perfect the process is super unforgiving, and intel is trying to navigate all that while putting out products that actually appeal to customers in different markets, planning them out at least a year in advance despite not having any idea what the market will look like in a year.

Moore's law is super dead. If any company were to manage to keep up it would be nothing short of a miraculous revival.

How are GPUs still apparently increasing their power exponentially without using more power? It looks like the best 10 series NVIDIA GPU has about twice the power of the best 9 series, about 2 years earlier, which lines up with Moore's Law pretty closely. How are they doing it? Maybe they were actually lagging Intel- looks like the 9 series was a 28nm process, and the 10 series is a 14 or 16nm process.

Yea, GPU's are a few nodes behind which means they will take longer to hit the same wall. Even the GTX 1080 Ti just hit 16nm.

Compare a 95 W (22nm) i7 2600k from January 2011 vs 65 W (14nm) Core i7-8706G from February 2018, that's over 7 years of progress for 30% lower power consumption and a fair speed boost.

That's what GPU's are facing starting now, though they can directly trade lower power consumption for more speed as they are embarrassingly parallel.

I can't answer authoritatively, but I would speculate it has to do with the highly parallel nature of GPUs.

That and dark silicon: https://en.wikipedia.org/wiki/Dark_silicon

Running a modern CPU with an acceptable TDP, means only so much of the transistors can be utilized simultaneously .

> Remember the 1960s when rapid gains in space tech made everyone think we'd be travelling around the solar system by 2000?

I think space tech is a different beast economically - the intensive had been more to compete for global dominance in the 1960s and not so much demand (from the general public) to travel in space. I believe there is a bigger intensive to have faster processors now but we might be hitting physical/engineering limitations so we go distributed.

An amazing 2014 talk[1]/article[2] by @idlewords explores exactly this premise.

[1] https://www.youtube.com/watch?v=nwhZ3KEqUlw [2] http://idlewords.com/talks/web_design_first_100_years.htm

Isn't nanometer scale also getting to the point that you're dealing with individual atoms? There is undoubtedly a point where you can't progress any further, and it seems reasonable that progress gets a lot harder as you approach that point.

In the biz people already measure some widths as "monolayers", which refers to a single layer of atoms. Some process features have error margins of less than a monolayer -- that is, a dieletric needs to be 4 monolayers thick, and if it only has 3, the device is going to short, and if it has 5, the device will not work.

What kind of CVD/PVD process do you use to achieve those kinds of tolerances? Or is the trick to use protect/deprotect steps like in conventional chemistry?

ALD is commonly used for these ultra fine tolerances.

Atoms in a silicon crystal are about 0.54 nm apart, so we are not quite there yet.

So you're saying a 10nm structure is about ~20 atoms long? So basically proving parents point...

No, saying that we are still an order of magnitude away from dealing with individual atoms. The current slowdown is more about light than about atoms; the move to EUV lithography [1] has proved to be very challenging [2].

[1] https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...

[2] https://spectrum.ieee.org/semiconductors/nanotechnology/euv-...

In theory Coulomb transistors can be a single molecule. I believe single molecule transistors have been experimentally demonstrated.

Anyway, around 5nm you start to have quantum tunneling effects. Current technology can't be scaled down much further. You can keep optimizing things, but you are still near the technology limits and increasing complexity.

Even though the numbers in process node names keep going down, this no longer directly corresponds to line widths. For example, the largest difference between TSMC 20nm and 16nm is that the way the transistor is built was completely changed.

There are a couple of transitions like this left that buy real performance and density, even if the actual line widths stay as they are, so there likely will be a "3nm" process node. After that, who knows.

Agree it might be possible, but still, my point is that gains become smaller and smaller, more and more complex, and you still don't end up with transistors an order of magnitude smaller.

I thought it was more that the money dried up, and the nuclear test ban prohibited testing of the sorts of nuclear rockets that were being prototyped at the time.

It's the same with semiconductors though, the barrier is mostly economical.

Has the budget for semiconductor research ever decreased? It's a tautology that we could be spending more money on it, but we are deeply investing in this field in a way that we stopped doing with space.

Is it? I was under the impression that we are hitting physical barriers, like transistor size getting closer and closer to Silicon atom size.

It's still technically possible to make chips with smaller nodes than the current mainstream processes allow, although this is uneconomical due to low yields and extremely thin margins.

Right, so "Moore's law is dead" really scoped to "... affordable, conventional materials and designs that we've almost finished wringing every scrap of ROI out of".

(That's not meant to be pejorative. Just saying I understand why companies would be loathe to ditch proven tooling w/ a lot of sunk costs).

To be more specific: the rumor is that integration of cobalt is the issue.

Can youbelaborate? What does cobalt have to do with the current nodes? And killer as in good or killer as in bad?

Sure, so Intel is using cobalt at low dimension interconnects (e.g. M0-3) because cobalt has lower resistance than copper at low dimensions due to electron mean free path issues.

The rumor is that integration of the cobalt material is what's causing yield issues at Intel for 10nm.

Why do we have to go below 10nm at all? We'll have hard physics limitations. Can't we improve on other frontiers? Say more cache?, better design ? More cores? Etc. I don't know.

Probably the #1 area that can produce results is avoiding/conquering the processor-memory gap: while processor performance has been growing exponentially, memory (bandwidth) performance has basically grown linearly. There is now a factor 1,000 difference between processor/memory speeds compared to 1980.

One of the areas that I have much hope for is near-data processing: since processors scale so much better, pretty much every peripheral device already has its own microcontroller. The idea behind NDP is basically to offload some data-heavy processing to the data layer. What if your disk layer could already preselect your data so the database wouldn't have to read and discard so many rows for each query? What if the network controller could evaluate your firewall rules itself, so dropped packets wouldn't have to interrupt the main CPU?

> What if your disk layer could already preselect your data so the database wouldn't have to read and discard so many rows for each query?

My impression is that that the process of filtering DB rows is sufficiently complex to need a full libc type execution environment. But taking a big step back in perspective, a famous example of filtering on processors connected to disks is Map-Reduce, aka Hadoop.

> What if the network controller could evaluate your firewall rules itself, so dropped packets wouldn't have to interrupt the main CPU?

Yes, this is a real thing: https://duckduckgo.com/?q=nic+packet+filter+offload

So NDP is essentially what Commodore did with their 1541 disk drive. That disk drive had a 6502 in there to complement the 6502 in the actual VIC-20.

From what I remember, the IBM System Z mainframes also do this sort of thing and have dedicated IO processors that can decode XML on the fly for you and other fun things like that.

As a matter of fact, I think this concept dates at least as far back as the IBM 360.

https://en.wikipedia.org/wiki/Channel_I/O

And you can find similar concepts in a standard PC today. The GPU is an example of offloading a workload to a specialized processor.

In addition, if each individual unit of memory hardware gained mini-CPU-like data processing capability, then you would have additional faux-CPU power that scaled linearly with memory; this would allow you to do some (embarassingly parallel) things much faster than just having one additional CPU per peripheral.

Every modern hard drive is a computer in its own right.

Seagate had a cool project where each hard drive ran linux and they used the physical sas cable to run a 2.5 Gbit network (or two actually) per drive.

So you could use that as block storage for luster, hadoop, or similar and enable things like direct disk to disk copies.

Cool idea, seems unlikely to hit a reasonable price point though.

This is first time I'm hearing it but NDP seems really cool. I like the idea of augmenting the memory and peripheral devices with intelligence.

Is Kryder's Law also dead? (2x memory every 13 months) If not, we could plan for petabyte local memory by 2030 and exabytes 2040s.

Making features smaller is far and away the most cost efficient way to make processors faster.

It is also relevant to remember fan size and processor design are at least two independent divisions in the same company (Intel, Samsung) and are often two separate companies (AMD, TSMC). Its not like the chip makers arent investing engineers in design.

I see. I wonder what there strategy would be like? To double the efforts in reducing fab size or in other factors.

We can of course do both, and there is a lot of work on improving the designs. But scaling down the transistor size is generally a wonderful thing: smaller transistors use less power, produce less heat, and you can fit way more of them in the same area (which enables things like larger caches, etc.)

Dennard scaling has been dead for a while, smaller transistors don't necessarily by default use less power anymore.

ok so I see that reducing fab size gives lot of benefits and they have steadily done so for past couple of decades. In doing so maybe they overlooked on design or other factors? And now that we've hit the wall on fab sizes (purportedly), maybe they can double their efforts on other factors.

That reminds me of this talk from 2013:

https://www.youtube.com/watch?v=JpgV6rCn5-g

The gist of it, as I remember it, is that radical design ideas were a bad investment while Moore's law ruled, because they were likely to be outperformed by simply shrinking the standard architecture; after Moore, design gains in importance, but don't expect anything like the performance improvements of the past half century.

Makes sense. Thanks for the video.

I think there really is quite a lot of innovation going on under the radar in the SoC space. Phones now have “neural engines” and all kinds of image-related processors for their cameras. Desktop CPUs come with integrated GPUs and there’s a lot of memory system consequences of that...

We are software limited also. AFAIK you could design a high level easy to use programming language with high performance vectorized array operations, but such languages at least are not in wide use. By high level I mean something like Ruby where you could specify lambdas for enumerables. But the vm would take care of vectorization and/or parallelization for you.