That's a fun idea! RV32E is 512 bits of general-purpose registers, RV32I is 1024, and RV64I is 2048. AVX-512's ZMM registers total 16384 bits. So you could have, say, a 4096-bit register which you could access as any of 13 different sizes, from 1 bit up to 4096.

I think the on-chip bus interconnect and ALU are probably going to have some finite width, though. Above that number of bits in an operation, your instructions will get slower. Maybe that's what you have in mind, and you just want to abstract that away?

This seems to be very close to RVV in terms of expressive power. The operations are going to be map,fold,filter

Don't forget scan!

An use of SIMD in x86 is fast ram copy/filling by sending all Avx register to ram with one instruction.

But I'm thinking more about having multiple logical CPUs, ALUs, or ports working on a single giant register. I think SIMD wastes a lot of hardware.

Example: radix sort needs to calculate a prefix sum. As the sum accumulates, it requires more bits, so the bit length should be adjustable. On x86, you can cast an array of bytes to a uint64_t and calculate eight prefix sums with a single multiplication. But eventually, you run into SWAR lane overflow problems. Ask an AI what this means and how the code works.

We need a CPU designed to handle lane overflow and dynamically adapt bit lengths, so at the start we do more parallel sums with less bits, and as the sum accumulate we increase the bit length gradually. This is just a simple use case. We could store more prefix sums as a periodic sum more deltas.

Such a CPU is not difficult to design, but the problem is that for the majority of the applications it would be much slower than a traditional CPU, by having a much lower clock frequency, caused by the additional delays through a great number of multiplexers and buffers that would be needed in such a CPU (even the multiplexers that are not implemented with physical gates, but e.g. with tri-state buffers driving common bit lines, introduce extra delays due to driving greater capacitances).

Besides a lower clock frequency, such a CPU would also have a power consumption, due to a greater total capacitance of the internal nodes.

The number of problems whose solution could be accelerated by such a structure is too low to make it worthwhile.

You want RAM?

How to make a chip designer's life a living hell 101.

That's fascinating! I've always wondered about whether there has ever been a cpu or if it'd be too difficult to build, that has 2 bit run-length registers. 1st bit -> value, 2nd bit -> has next. For processing arbitrary length data. Any size integer or string. It's not without a cost of course, but I find the idea of having a single atomic datatype of any length kind of nice.

I think you could probably adapt the SERV design to do this. You'd end up with a tiny but kinda slow core,

You'd essentially have a 1 bit processor with a cache that translated groups of bits to whatever memory access width was. CPUs already fill cache lines with transfers wider than registers, so the theory is there.

There's always a sweet spot for bang-for-buck on any tunable size like that. I doubt it is at 1-bit unless you can figure out how to do cache coherency with a few million cores.

Similar to my thoughts about having memory being bit addressable instead of being forced at byte boundaries. I am aware that this is inefficient but we have seen CPUs for example do byte addressing even thought they actually read words.