Re:$30M Raised to Redo the CPU
by Lerc on Wednesday November 11, 2026 @04:21AM
(#50451259)
I think you could probably adapt the SERV design to do this. You'd end up with a tiny but kinda slow core,
You'd essentially have a 1 bit processor with a cache that translated groups of bits to whatever memory access width was. CPUs already fill cache lines with transfers wider than registers, so the theory is there.
There's always a sweet spot for bang-for-buck on any tunable size like that. I doubt it is at 1-bit unless you can figure out how to do cache coherency with a few million cores.
You'd essentially have a 1 bit processor with a cache that translated groups of bits to whatever memory access width was. CPUs already fill cache lines with transfers wider than registers, so the theory is there.
There's always a sweet spot for bang-for-buck on any tunable size like that. I doubt it is at 1-bit unless you can figure out how to do cache coherency with a few million cores.