Such a CPU is not difficult to design, but the problem is that for the majority of the applications it would be much slower than a traditional CPU, by having a much lower clock frequency, caused by the additional delays through a great number of multiplexers and buffers that would be needed in such a CPU (even the multiplexers that are not implemented with physical gates, but e.g. with tri-state buffers driving common bit lines, introduce extra delays due to driving greater capacitances).

Besides a lower clock frequency, such a CPU would also have a power consumption, due to a greater total capacitance of the internal nodes.

The number of problems whose solution could be accelerated by such a structure is too low to make it worthwhile.