Such a CPU is not difficult to design, but the problem is that for the majority of the applications it would be much slower than a traditional CPU, by having a much lower clock frequency, caused by the additional delays through a great number of multiplexers and buffers that would be needed in such a CPU (even the multiplexers that are not implemented with physical gates, but e.g. with tri-state buffers driving common bit lines, introduce extra delays due to driving greater capacitances).
Besides a lower clock frequency, such a CPU would also have a power consumption, due to a greater total capacitance of the internal nodes.
The number of problems whose solution could be accelerated by such a structure is too low to make it worthwhile.
But I'm thinking more about having multiple logical CPUs, ALUs, or ports working on a single giant register. I think SIMD wastes a lot of hardware.
Example: radix sort needs to calculate a prefix sum. As the sum accumulates, it requires more bits, so the bit length should be adjustable. On x86, you can cast an array of bytes to a uint64_t and calculate eight prefix sums with a single multiplication. But eventually, you run into SWAR lane overflow problems. Ask an AI what this means and how the code works.
We need a CPU designed to handle lane overflow and dynamically adapt bit lengths, so at the start we do more parallel sums with less bits, and as the sum accumulate we increase the bit length gradually. This is just a simple use case. We could store more prefix sums as a periodic sum more deltas.