No is a good first approximation.

There is a little bit of industry usage, with the biggest user being SiFive - the founders come from the UC Berkeley group that developed Chisel.

Also, VexRiscv has some industry presence.

> There is a little bit of industry usage, with the biggest user being SiFive

do ask sifive how much they regret that decision though <shrug>

This is off topic, but I recognize your username from a thread a couple weeks ago but your account is relatively new. Out of curiosity did you just find hacker news and decide to make an account, or is this a new alias and you have an older account? I guess I'd be surprised if there's still new people joining lol.

my account is 8 months old? also i'm sure new people join hn all the time because you know... new people are being born all the time...

I was just wondering. It seemed like you had a perspective that I wouldn't associate with someone new to the industry.

I have no idea who they are, but I think you'd find there are lots of "old-timers" (even notable ones) who've never had HN accounts. Any of them could decide to join at any moment

I'm pretty sure they're going to say they don't regret it at all. Either because it's true, or because they are too invested in it.

When I've started doing FPGA consulting a few years ago I've started using Chisel, but eventually had to go back to SystemVerilog due to client reluctance.

I was dramatically more productive with Chisel than with SystemVerilog.

> I'm pretty sure they're going to say they don't regret it at all.

i didn't say that as a supposition - i know that they regret it. the chisel compiler has been an enormous (enormous) technical debt/burden for them because of how slow/resource intensive it is.

> how slow/resource intensive it is

compared to what?

It's not like all the other EDA tools are really fast or not resource intensive. For smaller design firms I would think things like FireSim [1] would be a significant advantage.

I can imagine it is a disadvantage in other ways, i.e. it's only possible to do single phase positive edge synchronous design, which could be an impediment to high performance digital design.

But I wouldn't imagine that scala performance is particularly significant.

[1] https://fires.im

It's pointless to argue with people on hn because you'll tell them "I have cold hard experience" and they'll respond with hype links and conjecture.

> But I wouldn't imagine that scala performance is particularly significant.

Imagine all you'd like - reality is much less imaginative though.

Just curious, do they have a migration plan? Have they started new designs using Verilog/SystemVerilog/VHDL?

Interesting. So, do you know what they'd choose now if they started over? SystemVerilog?

In the ASIC space, sure, I don't think any of these tools scale in the way that most ASIC companies have forced their "traditional" HDL toolchains to scale.

In the FPGA-based space (accelerators, RF/SDR, trading), hard disagree. There's plenty of boutique FPGA work going on in these.