Re:A FPGA friendly 32 bit RISC-V CPU implementation
by bri3d on Saturday January 25, 2025 @06:14PM
(#42825929)
In the ASIC space, sure, I don't think any of these tools scale in the way that most ASIC companies have forced their "traditional" HDL toolchains to scale.
In the FPGA-based space (accelerators, RF/SDR, trading), hard disagree. There's plenty of boutique FPGA work going on in these.
In the FPGA-based space (accelerators, RF/SDR, trading), hard disagree. There's plenty of boutique FPGA work going on in these.