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A comment on A FPGA friendly 32 bit RISC-V CPU implementation. Parent comment

Re:A FPGA friendly 32 bit RISC-V CPU implementation by oldgradstudent on Sunday January 26, 2025 @04:10PM (#42834176)
Just curious, do they have a migration plan? Have they started new designs using Verilog/SystemVerilog/VHDL?
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