A FPGA friendly 32 bit RISC-V CPU implementation

Re:A FPGA friendly 32 bit RISC-V CPU implementation by foota on Saturday January 25, 2025 @04:17PM (#42824933)

This is off topic, but I recognize your username from a thread a couple weeks ago but your account is relatively new. Out of curiosity did you just find hacker news and decide to make an account, or is this a new alias and you have an older account? I guess I'd be surprised if there's still new people joining lol.

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by almostgotcaught on Saturday January 25, 2025 @05:20PM (#42825485)

my account is 8 months old? also i'm sure new people join hn all the time because you know... new people are being born all the time...

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by foota on Saturday January 25, 2025 @06:50PM (#42826199)

I was just wondering. It seemed like you had a perspective that I wouldn't associate with someone new to the industry.

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by skissane on Saturday January 25, 2025 @07:04PM (#42826288)

I have no idea who they are, but I think you'd find there are lots of "old-timers" (even notable ones) who've never had HN accounts. Any of them could decide to join at any moment

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