As you said, I'm not sure about the density part. Unless it's completely done in BEOL, I don't see designers trade precious chip real estate for memory (unless pin or power-limited, of course).
What do you think on FRAM vs. next generation MRAM?
Well, hafnium can be used to make ferroelectric crystals, that are necessary for ferroelectric memories (FRAM). The most used ferroelectric material is PZT, which has lead, and is a nightmare for CMOS compatibility due to contamination issues, and temperatures.
It's a bit light on the details, but maybe I should point you towards the video that explains our project: https://www.youtube.com/watch?v=M8tL-nN7G-A
The most exciting part might not be the performance (though it looks good), but the way ferroelectrics can be used for new circuits (variable treshold transistors thanks to FeFETs). Hafnium has been used in gate oxides for a few years now so it's quite compatible with CMOS.
A very curious case, and a very clever hackery with a custom SOI process. It's still very, very far from coming to mainstream chips.
"Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM."
No word on latency though.
So if you just first make CMOS, and leave empty space nearby protected by something to do DRAM later, it will be very hard to fit into the tiny remaining thermal budget past which CMOS devices will turn into schmoo.
[a]: what’s the upper limit? As in, when does it not work anymore? For example, would it work at 100+ nm?
First, you need a wafer on which you can make a capacitor, which already means an SOI process, and SOI wafers.
The lowest nodes with SOI available to mortals are 40nm, and 14nm on GlobalFoundries, but god knows how one gets GloFo to collaborate on that.
Then, you need CMOS device which has enough thermal budget to survive both own, and DRAM creation.
Third, I think on-die DRAM will only make sense when it wins over SRAM. DRAM cells cannot physically go smaller than the minimal size of a trench capacitor. I believe at 5-7nm nodes, 6T SRAM will already be smaller than a reasonably fast eDRAM per area.
We know that IBM's Z15 is a 14nm FinFet chip, and it has DRAM on board, with them probably somehow doing DRAM first.
DRAM is incompatible with the logic family used in CPU making, though attempts were numerous at trying to work around that. Every few years, there are somebody coming with claims of passable CMOS+DRAM tech, but none got adoption so far.