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A comment on AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at 2 TB/SEC. Parent comment

Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by baybal2 on Tuesday June 01, 2021 @03:47AM (#27351683)
Not L1, but L2 and on.

A very curious case, and a very clever hackery with a custom SOI process. It's still very, very far from coming to mainstream chips.

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by jahnu on Tuesday June 01, 2021 @06:45AM (#27352685)
It says L1 here

"Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM."

https://en.m.wikipedia.org/wiki/IBM_z15_(microprocessor)

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by baybal2 on Tuesday June 01, 2021 @06:55AM (#27352753)
I got L1 being SRAM from here https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...
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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by jahnu on Tuesday June 01, 2021 @09:33AM (#27354160)
IBM's technical guide also says it's eDRAM

https://www.redbooks.ibm.com/redbooks/pdfs/sg248851.pdf

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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by rbanffy on Tuesday June 01, 2021 @01:41PM (#27358356)
It's almost sad to see the x86s compared to the IBM mainframes...
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Re:AMD Demonstrates Stacked 3D V-Cache Technology: 192 MB at... by amelius on Tuesday June 01, 2021 @01:49PM (#27358490)
What is the main hurdle? Why are these processes incompatible?
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