>" Shuttle runs are really only used to get samples for the first version of your chip."

Is a "tape out" the same thing as a shuttle run/sample chip run?

The only difference between a shuttle run and mass production is whether your chip is repeated 100 times in different parts of the wafer (surrounded by other people's chips) or a few thousand times completely covering the wafer with copies of just your chip.

The manufacturing process is identical either way.

Interesting fact, the term tape out comes from the way chips were physically laid out back in the early days. The chip layout was manually arranged using pieces of coloured tape on a large workspace/table. Once complete, this was photographed a layer at a time, which was then optically reduced to create the mask sets for manufacture. We still use the term tape out today, but no tape involved. I would love to have an experience of designing back during those days, it's so hands on.

Fascinating. So was each mask in a mask set individually taped to the work surface one at a time in order to be photographed?

a "tape out" is the process of transforming a design into a physical die - i.e. a manufacturing run. It's when you hand over a design to a foundry to do their thing with it.

Out of curiosity - what software is being used to design chips? Is there anything within reach of a small company, or something open source?

Front-end is HDLs — (System)Verilog, VHDL, etc. Implementation and formal will be Jasper & its ilk. Backend (physical, etc.) use fab-specific bespoke software from the majors (Cadence, NXP, MG, Synopsis, ...).

The front-end stuff could be done by one person; Verilator is a great example (although it's now "in house" to NXP). Implementation, LEC, etc. are mathematically intimidating -- they're proof engines -- but doable by a small team.

Physical requires inside knowledge of the fabs. The fabs aren't going to let you participate unless you're a major, because it costs them a lot of money, and each additional participant is another potential leak of their critical IP.

The tooling is all "vertical" and starts on the backend. If you can't do backend, you're not a player.

> The front-end stuff could be done by one person; Verilator is a great example (although it's now "in house" to NXP).

Huhwhatwho?

Verilator is in-house for NXP? When did that happen?

Verilator is still open source; some of the authors work at NXP and/or supported by NXP.

The commercial tools are indeed very expensive but the required data files can be as much of a problem. Normally you have to sign a bunch of NDAs (non disclosure agreements) to get your hands on the design rules and standard cell libraries supplied by the foundries and required to make the tools work.

One effort to organize several previously available open source tools into a practical system is OpenLane, which is based on the DARPA OpenRoad project:

https://woset-workshop.github.io/PDFs/2020/a21.pdf

Recently, Google has financed a project where a foundry has made its data files available without any NDAs:

https://github.com/google/skywater-pdk

The combination has made it possible to have completely open source chip designs.

Sounds like OSH Park for silicon...

Anyway, I'm still not sure why SiFive is doing this. Seems like a waste of money even as a prototype

SiFive is in the business of selling IP cores and back-end implementation services. The gold standard for IP core validation is "silicon proven" i.e. that it's not just a nice theoretical design on paper, but someone has actually turned it into a physical chip and tested the real life performance.

Lots of people will try to sell you their designs and services. Picking the wrong ones can waste millions of dollars and months/years of time.

The money spent on this a prototype buys SiFive credibility for both aspects of their business (assuming the chip works) - "we were able to do this for ourselves, so you know we'll be able to do it for you".

So it's not a waste, it's a marketing expense, and a necessary one.

The article mentions that is is from the OpenFive division of SiFive. OpenFive used to be Open Silicon and their business model was working with other companies to take their Verilog RTL and do all of the physical design (synthesis to logic gates, place and route of the standard cells, timing analysis, test vector generation) and then work with the foundries to deliver all of the data for manufacturing.

Since Open Silicon is now OpenFive and part of SiFive they literally have all this experience in house and don't need to depend on another company between them and TSMC.

https://en.wikipedia.org/wiki/Open-Silicon