Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by brucehoult on Saturday April 17, 2021 @07:40PM
(#26848419)
The only difference between a shuttle run and mass production is whether your chip is repeated 100 times in different parts of the wafer (surrounded by other people's chips) or a few thousand times completely covering the wafer with copies of just your chip.
The manufacturing process is identical either way.
Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by tails4e on Sunday April 18, 2021 @04:42PM
(#26856162)
Interesting fact, the term tape out comes from the way chips were physically laid out back in the early days. The chip layout was manually arranged using pieces of coloured tape on a large workspace/table. Once complete, this was photographed a layer at a time, which was then optically reduced to create the mask sets for manufacture. We still use the term tape out today, but no tape involved. I would love to have an experience of designing back during those days, it's so hands on.
Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by bogomipz on Monday April 19, 2021 @08:38PM
(#26869466)
Fascinating. So was each mask in a mask set individually taped to the work surface one at a time in order to be photographed?
Is a "tape out" the same thing as a shuttle run/sample chip run?