Front-end is HDLs — (System)Verilog, VHDL, etc. Implementation and formal will be Jasper & its ilk. Backend (physical, etc.) use fab-specific bespoke software from the majors (Cadence, NXP, MG, Synopsis, ...).

The front-end stuff could be done by one person; Verilator is a great example (although it's now "in house" to NXP). Implementation, LEC, etc. are mathematically intimidating -- they're proof engines -- but doable by a small team.

Physical requires inside knowledge of the fabs. The fabs aren't going to let you participate unless you're a major, because it costs them a lot of money, and each additional participant is another potential leak of their critical IP.

The tooling is all "vertical" and starts on the backend. If you can't do backend, you're not a player.

> The front-end stuff could be done by one person; Verilator is a great example (although it's now "in house" to NXP).

Huhwhatwho?

Verilator is in-house for NXP? When did that happen?

Verilator is still open source; some of the authors work at NXP and/or supported by NXP.

The commercial tools are indeed very expensive but the required data files can be as much of a problem. Normally you have to sign a bunch of NDAs (non disclosure agreements) to get your hands on the design rules and standard cell libraries supplied by the foundries and required to make the tools work.

One effort to organize several previously available open source tools into a practical system is OpenLane, which is based on the DARPA OpenRoad project:

https://woset-workshop.github.io/PDFs/2020/a21.pdf

Recently, Google has financed a project where a foundry has made its data files available without any NDAs:

https://github.com/google/skywater-pdk

The combination has made it possible to have completely open source chip designs.