3D NAND is successful and cost-effective because it's made by depositing dozens of layers at a time, then etching at the end of the process. Currently Samsung is in the lead by doing ~128L at a time. All their competitors reach 100+ layer counts by splitting the stack into two decks, eg. Micron's 176L NAND is 88+88.

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3d nand manufacturing steps

It's a pretty clever arrangement, in this layman's opinion.

That was very interesting!

Could these techniques be applied to logic circuitry too or is there something preventing that?

Logic circus don’t have the concept of word and bit lines - metal layers are much much more complex. And it’s inherently less economical to stack transistors because you would have to repeat many steps for every layer.

I get that the connection between each gate wouldn't be as uniform as in storage. I guess my question isn't can the exact technique be used, but rather the same principles/ideas.

I guess its hard to etch all the different connections between gates if they're not uniform?

But they still have to do multiple steps per layer to attach the per-layer connections at the edge?

Yeah, forming the staircase at the edge of the memory array is a big deal with a lot of steps, and it can take up a significant chunk of die area. But they can apparently do it with a very small number of photolithography masks: https://www.techinsights.com/webinar/memory-process-webinar-...