Re:SK hynix begins offering samples of 176-layer NAND chip (...
by londons_explore on Wednesday February 03, 2021 @06:11AM
(#26012605)
But they still have to do multiple steps per layer to attach the per-layer connections at the edge?
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Re:SK hynix begins offering samples of 176-layer NAND chip (...
by wtallis on Wednesday February 03, 2021 @11:27AM
(#26015233)
Yeah, forming the staircase at the edge of the memory array is a big deal with a lot of steps, and it can take up a significant chunk of die area. But they can apparently do it with a very small number of photolithography masks: https://www.techinsights.com/webinar/memory-process-webinar-...