Re:SK hynix begins offering samples of 176-layer NAND chip (...
by dkersten on Wednesday February 03, 2021 @12:50PM
(#26016568)
I get that the connection between each gate wouldn't be as uniform as in storage. I guess my question isn't can the exact technique be used, but rather the same principles/ideas.
I guess its hard to etch all the different connections between gates if they're not uniform?
I guess its hard to etch all the different connections between gates if they're not uniform?