News for hackers. Stuff that matters.
Re:SK hynix begins offering samples of 176-layer NAND chip (... by ohazi on Tuesday February 02, 2021 @11:42PM (#26010675)
Re:SK hynix begins offering samples of 176-layer NAND chip (... by dkersten on Wednesday February 03, 2021 @08:23AM (#26013367)
That was very interesting!

Could these techniques be applied to logic circuitry too or is there something preventing that?

Re:SK hynix begins offering samples of 176-layer NAND chip (... by xadhominemx on Wednesday February 03, 2021 @10:10AM (#26014257)
Logic circus don’t have the concept of word and bit lines - metal layers are much much more complex. And it’s inherently less economical to stack transistors because you would have to repeat many steps for every layer.
Re:SK hynix begins offering samples of 176-layer NAND chip (... by dkersten on Wednesday February 03, 2021 @12:50PM (#26016568)
I get that the connection between each gate wouldn't be as uniform as in storage. I guess my question isn't can the exact technique be used, but rather the same principles/ideas.

I guess its hard to etch all the different connections between gates if they're not uniform?