I’d guess that the upper limit is stability rather than thermal capacity at that point

What does stability mean, a bit more exactly? Just curious

The switching speed of silicon has also some upper limit. When you drive silicon faster, it starts to make mistakes. i.e. not all electrons go the where you want them to go. This causes soft-faults and CPU re-executes the part at best, or gives you a BSOD, oops or panic at worst.

This upper limit depends on process, layout, power design and power limits of the CPU.

Last but, not the least, not all CPUs are created equal on a wafer. I came from an era where we hunted plain blue AMD Athlon dies for higher overclocking potential, since they were from center of the wafer and they were more stable under high load/voltage/clock. I had a 2200MHz Athon (200 x 11) which was faster then AMD's own 2200MHz Athlons, since AMD wasnt offering a 200MHz bus version of their 2200MHz parts.

>gives you a BSOD, oops or panic at worst.

That's not too bad. I'd be much more worried about code silently doing the wrong thing .

That happens too. Prime 95 and other stability tests are used and can check when wrong results are returned. There's often a sliver of frequencies where a system under load begins performing floating point calculations incorrectly while other, simpler systems in the CPU are still functioning correctly.

The BSOD, oops, or panic is a symptom of widespread errors.

That's also possible. That's why overclockers run Prime95 to test their CPU stability.

Also, a BSOD or panic in the wrong time can cause massive data loss. That's beyond bad sometimes.

Edit: I mixed Prime95 with SuperPi. Thanks AaronFriel.

Why do you think the panic happens?

It's because the code does the wrong thing, and that happens silently... until it hits some pointers or kernel structures and stops being silent.

Not always. CPUs have extensive "machine check" capabilities. some of these MCE events are recoverable, some not.

If the processor fires an unrecoverable MCE event, you're frozen with a nice, explanatory panic.

Why are chips in the centre plain blue and better?

Plain blue is not a reason but a result.

Center of a silicon wafer is said to be have a higher quality (due to lithography, physical stresses and other processes which I don't know exact details of), and the result is a die with more homogeneous properties and color reflection. Since the die's tolerances were lower around the center of the wafer, the performance of the resulting chip was better.

AMD was also sub-binning most of these parts (they were sold as Athlon 1700 @ 1433MHz regardless of their performance level), so people were buying these unlocked sleepers and overclocking them to insane levels without voltage increases.

However, today the processes is so different and node sizes are so small that the dies' color are different and not perceivable anyway.

In the older days, this issue was more of an obscure, collective wisdom which resulted from trial and error days of overclocking wars.

Disclaimer: this is an oversimplification and I only have a lay person's understanding.

CPUs are basically huge networks of transistors (on/off switches). They're sort of like tiny printed circuit boards; lots of individual 'parts' are connected by 'wires' on top of a silicon wafer.

The distances are miniscule, but the lengths of wires running between transistors still varies. So when a transistor switches between 'off' and 'on', the signal takes a different amount of time to reach to its destination depending on which transistors are being switched. The signal can also feed into multiple other transistors which it will reach at different times.

While signals are busy propagating through the circuit, the CPU's state will be unstable, including the 'output' value of its current instruction. The time that it takes for any given instruction to stabilize is tough to predict because it depends on a lot of things, including how far apart the transistors are and how many of them the signal needs to pass through.

The CPU's "tick rate" in Hertz relates to how quickly it "latches" its internal state. Between "ticks", the CPU waits for all of the signals to stabilize. If they haven't stabilized when the clock strikes, bad things can happen.

I'm not sure how the 'quality' of an individual chip can make it more amenable to overclocking, though; maybe they run into fewer issues from thermal stress? Maybe the tiny 'wires' between the transistors have slightly less resistance? I dunno, someone help me out?

I think the inconsistencies between samples of the same model of chip are much less about the interconnect wires than about the transistors themselves, having variation in their individual switching speed vs voltage curves. There's nor really much variation in interconnect length between a given two gates when both chips are made from the same masks. But especially at the lower (finer pitch) layers of metal interconnect, variations in resistance and capacitance can affect how things operate.

The CPU not losing its marbles when overclocked.

https://devblogs.microsoft.com/oldnewthing/20050412-47/?p=35...

Knowing nothing can reduce performance from peak can be more valuable than an extra 4%

Yeah it's weird. Why not set the single-core turbo higher?

Marketing.

I believe Intel processors can't boost all cores. At least some tests I have done with my notebook processor (i7 8550u - 4c8t) with `stress -c n`, being n the number of processors, show that for n > 1 the processor doesn't reach 4ghz, only about 3.7ghz, while the package temps are still at around 70 °C. Only a single core on full load reaches 4ghz before throttling.

This is entirely configurable. They generally don't do all core == max boost for power consumption reasons (and I assume yield would be pretty low on chips that can do this)

Desktop chips also generally don't have any AVX offset, which is almost always required for 5 GHz all core.

Yes, there's a table in the firmware that can tell you the maximum speed with N active cores. This one though has the same speed for all values of N.

> I believe Intel processors can't boost all cores.

And that's exactly what shereadsthenews's point is. They can't boost all cores, and they are not boosting any core beyond the all-core capacity if it's truly a CPU that runs at 5 GHz all the time.

Turbo Boost can certainly apply to all cores- the limits you hit are TDP and time based, there, not strictly thermal.

So, for example, my old laptop CPU would clock itself up to 2.7GHz on all cores... well, okay, it was a dual core, so that's not saying much, but still. But it'd only maintain that boost for a few seconds- under sustained load it dropped down to 2.5. This wasn't because of thermals, but rather because 2.7GHz was a Turbo Boost frequency, and once the PPL timer runs out...

And to explain why they don't have, say, one core boost to 5.1GHz...well, let's see what siliconlottery says.

> As of 3/16/19, the top 38% of tested 9900Ks were able to hit 5.0GHz or greater.

> As of 3/16/19, the top 8% of tested 9900Ks were able to hit 5.1GHz or greater.

So, Intel'd cut their yield by more than a factor of four if they only let parts that could hit 5.1 into this bin. For a 2% single-core performance boost...

I think those numbers are for chips that can 5.1 GHz all core though, which is probably a lot less than 5.1 GHz single core.

As far as I know, K-series parts don't support binning of individual cores- if you have one bad core that'll only hit 5.0, 1-core turbo to 5.1 will still result in the OS scheduler periodically picking that core to use, it clocking up to 5.1, and problems resulting.

Might be wrong, though.

Intel's Turbo Boost 3.0 [1] was their attempt to take advantage of the fact that some cores on a chip can clock higher than others. It does not work well in practice, because it requires too much collaboration with motherboard and OS vendors. This feature is not available on their desktop platform, which the i9-9900KS uses.

[1] https://www.intel.com/content/www/us/en/architecture-and-tec...

XTU allows setting different turbo multipliers for 1-4 active cores (but the difference from the nominal clock speed typically gets smaller as more cores become active).