> The fact that digital logic design is constrained to one of two ancient languages by the proprietary toolsets is a serious problem.

Not really. You can compile any high-level language to a netlist and use that as input for place&route. Even if the proprietary toolchain didn't support EDIF netlists, you could still compile to a purely structural VHDL/Verilog file with the instantiated FPGA logic primitives (LUTs, nets, etc.), which is basically

The main (but not the only) reason why VHDL and Verilog have not been replaced yet, is that nearly all supposedly "better" alternatives fail to address the actual pain points in FPGA design. The most likely cause for this is that the overlap between professional FPGA designers and people capable and willing of designing and implementing a language is very, very small. The result is that you get a lot of languages designed by people who have never programmed larger FPGAs in a professional setting and consequently don't have a good understanding of the problems involved.

Do you have any good source of what these problems are? The reason I am asking is because I too am designing my home-grown HDL at the moment because I grew tired of both Verilog and VHDL. Since I never programmed FPGAs professionally -- the whole thing is a pet project only -- I'm likely to repeat those mistakes because I don't even know about them.

Note that I don't expect problems in the basics of language design and building tools, but rather specific mistakes in the context of FPGAs.

I'm curious to know more about your HDL, as I'm also working on an HDL of my own.

The code is at https://github.com/MartinGeisse/mahdl-plugin

Feel free to open an issue on GitHub to start a discussion. (I'm hesitant to post my private email address here -- old habits.)

It's actually kinda funny you mentioned designed without understanding FPGA development. VHDL predates FPGAs. Further, there are a lot of features that exist that are un-synthesizable. Some belong to the analog world. Some can't even be really even be used to build a real device.

Don't get me wrong – VHDL is a terrible language for design and verification (just like Verilog). Some of those new high-level languages are actually better than VHDL and Verilog, but not sufficiently better to overcome the momentum of the old languages.

> VHDL predates FPGAs

I was using "FPGA design" as a placeholder for digital logic design in general, given that by far the most VHDL and Verilog is written for FPGAs today.

Well, I kind of prefer VHDL.

Same. My main reason is Verilog does not make a distinction between variables and other objects. Verilog treats almost everything as if it were an assignment type. Furthermore, variables in verilog are shared by default. VHDL shows how it should be done. There is a clear distinction between signals and variables. Additionally, variables are local by default.

My opinion of course. Although VHDL can be bit more wordy. However, that's least of my worries (wordiness) when designing something. I would rather have clear semantics for me and other people on what the heck is going on.

There is SystemC, and that's not exactly ancient. It's handy when working at the architectural level.

Also what's wrong with old languages? Looks at C for instance which is much older than VHDL or Verilog.

SystemC and every other high level synthesis language, has to be translated to VHDL/verilog first. That's a big difference with software land.

HDLs are not bad, but not having the option to explore better options is bad

Not entirely true. You can generate netlists without going to VHDL/Verilog.