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A comment on Reverse-engineering FPGAs [video]. Parent comment

Re:Reverse-engineering FPGAs [video] by anfilt on Friday January 19, 2018 @06:09AM (#16185389)
There is SystemC, and that's not exactly ancient. It's handy when working at the architectural level.

Also what's wrong with old languages? Looks at C for instance which is much older than VHDL or Verilog.

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Re:Reverse-engineering FPGAs [video] by lvoudour on Friday January 19, 2018 @06:26AM (#16185440)
SystemC and every other high level synthesis language, has to be translated to VHDL/verilog first. That's a big difference with software land.

HDLs are not bad, but not having the option to explore better options is bad

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Re:Reverse-engineering FPGAs [video] by anfilt on Friday January 19, 2018 @06:34AM (#16185473)
Not entirely true. You can generate netlists without going to VHDL/Verilog.
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