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Re:Reverse-engineering FPGAs [video] by lvoudour on Friday January 19, 2018 @06:26AM (#16185440)
SystemC and every other high level synthesis language, has to be translated to VHDL/verilog first. That's a big difference with software land.

HDLs are not bad, but not having the option to explore better options is bad

Re:Reverse-engineering FPGAs [video] by anfilt on Friday January 19, 2018 @06:34AM (#16185473)
Not entirely true. You can generate netlists without going to VHDL/Verilog.