Show HN: A pipelined RISC-V processor written in VHDL

Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @06:13PM (#9964904)

Chisel by definition can ONLY generate synthesizable Verilog.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by rjsw on Tuesday July 28, 2015 @06:18PM (#9964928)

It wasn't doing for rocket when I tried building it at the weekend and won't even build RISC-V at all right now.

Feel free to fix it.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by gluggymug on Tuesday July 28, 2015 @07:36PM (#9965285)

There's two possibilities.

- Rocket has no automated build flow that checks whether committed code is synthesizable.

- you aren't using the same flow as them. I struggled to find what synthesis tools they used just now so I don't blame you!

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Re:Show HN: A pipelined RISC-V processor written in VHDL by rjsw on Wednesday July 29, 2015 @10:42AM (#9968941)

The code that is committed isn't directly synthesizable, it needs to be transformed to HDL by a tool that is itself being updated.

I tried what looked to be a supported flow, generate Verilog for FPGAs then synthesize it for Xilinx Zynq devices. The Verilog errors looked correct to me.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by gluggymug on Wednesday July 29, 2015 @03:28PM (#9971020)

I saw a little info on that at https://github.com/ucb-bar/fpga-zynq

I guess you are referring to that?

It's supposed to be a relatively mature tool so there's got to be a version that works ok.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @06:24PM (#9964964)

Then please submit an issue to the github issue queue. Don't complain on some internet forum and hope that somebody will read your mind. It works fine for me.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by rjsw on Tuesday July 28, 2015 @06:39PM (#9965042)

I don't have a github account.

I just suggested a reason why someone might choose to use a conventional HDL.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @07:21PM (#9965205)

Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the case, you should let them know.

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